FM21L16_11 RAMTRON [Ramtron International Corporation], FM21L16_11 Datasheet - Page 11

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FM21L16_11

Manufacturer Part Number
FM21L16_11
Description
2Mbit F-RAM Memory
Manufacturer
RAMTRON [Ramtron International Corporation]
Datasheet
Power Cycle and Sleep Mode Timing (T
Notes
1.
2.
Data Retention
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
Rev. 2.0
Apr. 2011
Symbol
t
t
t
t
t
t
t
t
t
Data Retention
PU
PD
VR
VF
ZZH
WEZZ
ZZL
ZZEN
ZZEX
Slope measured at any point on V
Ramtron cannot test or characterize all V
when V
100ms through the range of 0.4V to 1.0V.
DD
is below the level of a transistor threshold voltage. Ramtron strongly recommends that V
Parameter
Power Up (after V
Last Write (/WE high) to Power Down Time
V
V
/ZZ Active to DQ Hi-Z Time
Last Write to Sleep Mode Entry Time
/ZZ Active Low Time
Sleep Mode Entry Time (/ZZ low to /CE don’t care)
Sleep Mode Exit Time (/ZZ high to 1
DD
DD
(V
Rise Time
Fall Time
DD
= 2.7V to 3.6V)
Parameter
0 to 3V
3 ns
DD
DD
min. is reached) to First Access Time
waveform.
DD
A
= -40 C to + 85 C, V
power ramp profiles. The behavior of the internal circuits is difficult to predict
st
access after wakeup)
Input and Output Timing Levels
Output Load Capacitance
Min
DD
10
= 2.7V to 3.6V unless otherwise specified)
Min
450
100
50
Units
Years
0
0
1
-
-
-
FM21L16 - 128Kx16 FRAM
Max
450
20
1.5V
30pF
0
-
-
-
-
-
-
Notes
DD
power up faster than
Units
s/V
s/V
ns
s
s
s
s
s
s
Page 11 of 15
Notes
1,2
1,2

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