MSS1048-152NL AD [Analog Devices], MSS1048-152NL Datasheet - Page 17

• Manufacturer Part Number: MSS1048-152NL
• Description: Dual 5 A, 20 V Synchronous Step-Down
• Manufacturer: AD [Analog Devices]

Data Sheet
BOOTSTRAP CIRCUITRY
The
drive voltage for the high-side NFETs. The regulators generate
5 V bootstrap voltages between the BSTx and the SWx pins.
It is recommended that an X7R or X5R, 0.1 μF ceramic
capacitor be placed between the BSTx and the SWx pins.
LOW-SIDE DRIVER
The DLx pin provides the gate drive for the low-side N-channel
MOSFET. Internal circuitry monitors the gate driver signal to
ensure break-before-make switching to prevent crossconduction.
The VDRV pin provides the power supply to the low-side drivers.
It is limited to a 5.5 V maximum input; placing a 1 μF ceramic
capacitor close to this pin is recommended.
OSCILLATOR
A resistor from RT to GND programs the switching frequency
according to the following equation:
A 200 kΩ resistor sets the frequency to 300 kHz, and a 100 kΩ
resistor sets the frequency to 600 kHz. Figure 46 shows the
typical relationship between f
SYNCHRONIZATION
The SYNC pin can be configured as an input or an output by
setting the SCFG pin, as shown in Table 5.
Table 5. SCFG Configuration
SCFG
INTVCC
GND
180 kΩ to GND
100 kΩ to GND
When the SYNC pin is configured as an output, it generates a
clock with a frequency that is equal to the internal switching
frequency.
ADP2325
f
1200
1000
SW
1100
900
800
700
600
500
400
300
200
[kHz] =
50
70
integrates the boot regulators to provide the gate
R
90
60
OSC
,
000
[
110
kΩ
Figure 46. f
]
130
SYNC
Output
Input
Input
Input
SW
R
OSC
and R
150
SW
(kΩ)
vs. R
170
OSC
OSC
.
190
Phase Shift
0°
90°
120°
60°
210
230
250
Rev. 0 | Page 17 of 32
When the SYNC pin is configured as an input, the
chronizes to the external clock that is applied to the SYNC pin, and
the internal clock must be programmed lower than the external
clock. The phase shift can be programmed by the SCFG pin.
When working in synchronization mode, the
the PFM mode and works only in the CCM mode.
SOFT START
Use the SSx pins to program the soft start time. Place a capacitor
between SSx and GND; an internal current charges this capacitor
to establish the soft start ramp. The soft start time can be calculated
using the following equation:
where:
C
I
If the output voltage is precharged prior to power-up, the
prevents the low-side MOSFET from turning on until the soft
start voltage exceeds the voltage on the FBx pin.
During soft start, the
prevent output current runaway. The switching frequency is
reduced according to the voltage present at the FBx pin, which
allows more time for the inductor to discharge. The correlation
between the switching frequency and the FBx pin voltage is listed
in Table 6.
Table 6. FBx Pin Voltage and Switching Frequency
FBx Pin Voltage
V
0.4 V > V
V
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The
prevent current runaway. Place a resistor between DLx and PGND
to program the peak current-limit value, as listed in Table 7.
The programmable peak current-limit threshold feature allows
for the use of a small size inductor for low current applications.
Table 7. Peak Current-Limit Threshold Setting
R
Floating
47 kΩ
The
When the peak inductor current reaches the current-limit
threshold, the high-side MOSFET turns off and the low-side
driver turns on until the next cycle while the overcurrent counter
is incremented.
SS
FB
FB
ILIM
SS
is the soft start pull-up current (3.5 μA).
≥ 0.4 V
< 0.2 V
is the soft start capacitance.
ADP2325
ADP2325
t
SS

FB
≥ 0.2 V
0
6 .
V
I
uses a peak current-limit protection circuit to
uses hiccup mode for overcurrent protection.
SS

Peak Current-Limit Threshold
8 A
4.8 A
C
SS
ADP2325
Switching Frequency
f
1/2 f
1/4 f
SW
SW
SW
uses frequency foldback to
ADP2325
ADP2325
ADP2325
ADP2325
disables
syn-