TS2GDOM40V TRANSCEND [Transcend Information. Inc.], TS2GDOM40V Datasheet - Page 35

• Manufacturer Part Number: TS2GDOM40V
• Description: 40-Pin IDE Flash Module
• Manufacturer: TRANSCEND [Transcend Information. Inc.]

Ultra DMA Sender and Recipient IC Timing Requirements
Name
t
t
t
t
t
t
t
t
Notes:
(1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.
(2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and
(3) The parameters t
Ultra DMA AC Signal Requirements
Note:
DSIC
DHIC
DVSIC
DVHIC
DSIC
DHIC
DVSIC
DVHIC
(1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The
Name
S
S
falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at t
through 1.5 V).
signals have the same capacitive load value. Noise that may couple onto the output signals from external
sources has not been included in these values.
Transcend Information Inc.
T
1
T
1
T
1
RISE
FALL
The test load and test points should then be soldered directly to the exposed source side connectors. The test
loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the
test point to ground. Slew rates shall be met for both capacitor values.
MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with
data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output high
level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent
falling edge.
Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500
signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point.
All other signals should remain connected through to the recipient. The test point may be located at any point
between the sender’s series termination resistor and one half inch or less of conductor exiting the connector.
If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut
within one half inch of the connector.
2
r
2
r
2
r
a
a
a
8
8
8
n
n
n
M
M
Recipient IC data setup time (from data valid until STROBE edge) (see note 2)
Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2)
Sender IC data valid setup time (from data valid until STROBE edge) (see note 3)
Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)
M
UDMA Mode 0 (ns) UDMA Mode 1 (ns) UDMA Mode 2 (ns) UDMA Mode 3 (ns) UDMA Mode 4 (ns)
s
s
s
B
B
B
14.7
72.9
c
c
Min
c
4.8
9.0
e
Rising Edge Slew Rate for any signal
Falling Edge Slew Rate for any signal
e
e
~
~
~
n
n
n
8
8
d
8
d
d
DVSIC
G
G
G
4
4
4
Max
B
B
B
0
0
0
and t
-
-
-
P
P
P
i
i
i
DVHIC
n
n
n
50.9
Min
9.7
4.8
9.0
Comment
I
I
I
D
D
D
shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all
E
E
E
F
F
Max
F
l
l
l
a
a
a
s
s
s
h
h
h
M
33.9
M
Min
M
6.8
4.8
9.0
35
o
o
o
d
d
d
u
u
u
l
l
l
Max
e
e
e
Min[V/ns]
22.6
Min
6.8
4.8
9.0
DSIC
and t
Max
Max [V/ns]
1.25
1.25
DHIC
timing (as measured
Min
4.8
4.8
9.5
9.0
Note
Max
1
1
Ver 1.7