TS2GDOM40V TRANSCEND [Transcend Information. Inc.], TS2GDOM40V Datasheet - Page 39

• Manufacturer Part Number: TS2GDOM40V
• Description: 40-Pin IDE Flash Module
• Manufacturer: TRANSCEND [Transcend Information. Inc.]

Host Pausing an Ultra DMA Data-In Burst
below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12:
Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
(b) The host shall pause an Ultra DMA data burst by negating -HDMARDY.
(c) The device shall stop generating DSTROBE edges within t
(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two
(e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY.
Notes:
(1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than t
(2) After negating -HDMARDY, the host may receive zero, one, two, or three more data words from the device.
(3) The bus polarity of the (-) DMARQ and (-)DMACK signals is dependent on the active interface mode.
burst has been transferred.
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host
shall be prepared to receive zero, one, two or three additional data words. The additional data words
are a result of cable round trip delay and t
Transcend Information Inc.
T
1
T
1
T
1
-HDMARDY is negated.
The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in
2
r
2
r
2
r
a
a
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
a
8
8
8
n
n
n
M
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
M
M
s
s
s
B
B
B
c
c
c
e
e
e
~
~
~
n
n
n
8
8
d
8
d
d
G
G
G
4
4
4
B
B
B
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
s
s
RFS
h
h
h
timing for the device.
M
M
M
39
o
o
o
d
d
d
u
u
u
l
l
l
e
e
e
RFS
of the host negating -HDMARDY.
RP
Ver 1.7
after