IDT70V65 IDT [Integrated Device Technology], IDT70V65 Datasheet - Page 19

• Manufacturer Part Number: IDT70V65
• Description: HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
4. A
Truth Table IV —
Address BUSY Arbitration
Functional Description
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT70V659/58/57 has an automatic power
down feature controlled by CE. The CE
power down circuitry that permits the respective port to go into a standby
mode when not selected (CE = HIGH). When a port is enabled, access
to the entire memory array is permitted.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V659/58/57.
2. There are eight semaphore flags written to via I/O
3. CE = V
Truth Table V — Example of Semaphore Procurement Sequence
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
X
H
X
L
IDT70V659/58/57 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
and enable inputs of this port. If t
when BUSY
be for A
The IDT70V659/58/57 provides two ports with separate control,
L
16
X
is a NC for IDT70V658, therefore Address comparison will be for A
CE
X
X
H
L
IH
0
R
, SEM = V
- A
Inputs
L
R
and BUSY
14
outputs are driving LOW regardless of actual logic level on the pin.
.
Functions
NO MATCH
A
A
OL
MATCH
MATCH
MATCH
OR
-A
IL
-A
16L
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
R
16R
(4)
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
APS
BUSY
(2)
H
H
H
is not met, either BUSY
L
Outputs
(1)
0
and CE
BUSY
D
0
(2)
H
H
H
0
- D
and read from all I/O's (I/O
R
1
L
1
1
1
1
1
1
1
(1)
35
0
0
0
0
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
control the on-chip
Left
Write Inhibit
L
or BUSY
Function
Normal
Normal
Normal
4869 tbl 17
D
0
R
- D
(3)
0
= LOW will result. BUSY
- A
35
1
1
1
0
0
1
1
0
1
1
1
19
15
Right
. Also, A
0
Interrupts
or message center) is assigned to each port. The left port interrupt flag
(INT
(HEX) (FFFE for IDT70V658 and 7FFE for IDT70V657), where a write
is defined as CE
the interrupt through access of address location 1FFFE (FFFE for
IDT70V658 and 7FFE for IDT70V657) when CE
-I/O
35
If the user chooses the interrupt function, a memory location (mail box
L
). These eight semaphores are addressed by A
) is asserted when the right port writes to memory location 1FFFE
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
16
X
and A
L
15
R
and BUSY
X
= R/W
Industrial and Commercial Temperature Ranges
are NC's for IDT70V657, therefore Address comparison will
R
R
= V
outputs can not be LOW simultaneously.
IL
per the Truth Table III. The left port clears
Status
0
- A
L
= OE
2
.
(1,2,3)
L
= V
IL
, R/W is
4869 tbl 18