TSS463-AAR ATMEL [ATMEL Corporation], TSS463-AAR Datasheet - Page 10

• Manufacturer Part Number: TSS463-AAR
• Description: VAN Data Link Controller with Serial Interface
• Manufacturer: ATMEL [ATMEL Corporation]

SCI Protocol
SCI Control Byte
Clocks and Speed
Considerations
SCLK and XTAL Clocks
Intel and Motorola SPI Modes
Figure 7. SPI Speed Considerations
SCI Mode
10
TSS463-AA
SCLK
MOSI
SS
(4 s at 1 MHz)
4 Xtal Min
4 Mbits/s Max for SCLK
Address
The Slave Select signal must not toggle between each transmitted byte and therefore,
should be left at a low level during the whole SCI frame. SS must be asserted to inactive
high level at the end of the SCI frame.
If SS is not asserted, MISO pin is in high impedance state and incoming data is not
driven to the serial data register.
Same as the SPI protocol described earlier except for data arranging (LSB first and
MSB last).
Only 8 bits are monitored by the TSS463AA and master must monitor the 8 first
bits too (9
Same as the SPI control byte.
The SPI/SCI speed rate is given by the CPU producing SCLK. XTAL clock controls the
speed rate on the VAN bus. The two clocks are asynchronous, but a minimum SPI/SCI
interframe spacing must be apply according to XTAL clock.
Within an SPI byte, the maximum speed allowed on the MOSI line is 4 Mbits/s.
For example, when using a 1 MHz oscillator (sufficient to provide 62.5 kTS/s on the VAN
bus) the minimum inter-character delay is 12 s (12 oscillator periods). Speed consider-
ations are detailed in Figure 7.
Within an SCI 9-bits data, the maximum speed allowed on the MOSI line is 125 Kbits/s.
When using a 1 MHz oscillator, the data transfer speed and the minimum delay time
between SCI bytes are shown on Figure 8.
8 Xtal Min
(8
th
s at 1 MHz)
bit always equal to 1).
Control
(15 s at 1 MHz)
15 Xtal Min
Data
(12 s at 1 MHz)
12 Xtal Min
4205B–AUTO–12/04