A40MX02-1BG100 ACTEL [Actel Corporation], A40MX02-1BG100 Datasheet - Page 41
A40MX02-1BG100
Manufacturer Part Number
A40MX02-1BG100
Description
40MX and 42MX FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A40MX02-1BG100.pdf
(123 pages)
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PCI System Timing Specification
Table 26
parameters and the corresponding timing parameters
for the MX PCI-compliant devices.
Table 26 •
Table 27 •
Symbol
t
t
t
Symbol
t
t
t
t
t
t
t
Notes:
1. T
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals.
CYC
HIGH
LOW
VAL
VAL(PTP)
ON
OFF
SU
SU(PTP)
H
GNT# has a setup of 10; REW# has a setup of 12.
OFF
is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
and
Parameter
CLK Cycle Time
CLK High Time
CLK Low Time
Parameter
CLK to Signal Valid—Bused Signals
CLK to Signal Valid—Point-to-Point
Float to Active
Active to Float
Input Set-Up Time to CLK—Bused Signals
Input Set-Up Time to CLK—Point-to-Point
Input Hold to CLK
Clock Specification for 33 MHz PCI
Timing Parameters for 33 MHz PCI
Table 27
list the critical PCI timing
10, 12
Min.
Min.
2
v6.0
30
11
11
2
2
–
7
0
2
2
PCI Models
Actel provides synthesizable VHDL and Verilog-HDL
models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Actel sales
representative for more details.
PCI
PCI
Max.
Max.
11
12
28
–
–
–
–
–
–
–
Min.
Min.
1.5
4.0
1.9
1.9
2.0
2.0
2.0
1.5
–
0
A42MX24
A42MX24
Max.
Max.
8.3
9.0
9.0
4.0
–
–
–
–
–
–
1
40MX and 42MX FPGA Families
Min.
Min.
4.0
1.9
1.9
2.0
2.0
2.0
1.5
1.5
–
0
A42MX36
A42MX36
Max.
Max.
8.3
9.0
9.0
4.0
–
–
–
–
–
–
1
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-35
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