A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet
A40MX02-PL208A
Related parts for A40MX02-PL208A
A40MX02-PL208A Summary of contents
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... Single-Chip ASIC Alternative Applications • 3,000 to 54,000 System Gates • 2.5 kbits Configurable Dual-Port SRAM • Fast Wide-Decode Circuitry • 202 User-Programmable I/O Pins Product Profile Device A40MX02 Capacity System Gates 3,000 SRAM Bits – Logic Modules Sequential – Combinatorial ...
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... A-grade parts are not tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing options available. Plastic Device Resources PLCC PLCC Device 68-Pin 84-Pin A40MX02 57 – A40MX04 – 69 A42MX09 – 72 A42MX16 – ...
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Table of Contents 40MX and 42MX Automotive FPGA Families General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Automotive FPGA Families General Description Actels' automotive-grade MX families provide a high- performance, single-chip solution for shortening the system design and development cycle, offering a cost- effective alternative to ASICs for in-cabin telematics and automobile interconnect applications. ...
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Automotive FPGA Families D00 D01 D10 S0 D11 7-Input Function Plus D-Type Flip-Flop with Clear 4-Input Function Plus Latch with Clear Figure 1-3 • 42MX S-Module Implementation Figure 1-4 ...
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WRAD[5:0] Latches MODE Write BLKEN Logic WEN WCLK Figure 1-5 • A42MX36 Dual-Port SRAM Block Routing Structure The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects ...
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Automotive FPGA Families Clock Networks The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK network by being routed through the CLKBUF buffer. In 42MX devices, there are two ...
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I/O Modules The I/O modules provide the interface between the device pins and the logic array. diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module. (Refer ...
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Automotive FPGA Families Power Supply Automotive MX devices are designed to operate in 5.0V environments. automotive MX devices. Table 1-1 • Voltage Support of Automotive-Grade MX Devices Device CCA 40MX 5.0V – 42MX – ...
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Serial Connection to Windows PC Figure 1-11 • Silicon Explorer II Setup with 40MX Serial Connection to Windows PC Figure 1-12 • Silicon Explorer II Setup with 42MX Table 1-2 • Device Configuration Options for Probe Capability Security Fuse(s) Programmed ...
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Automotive FPGA Families Design Consideration It is recommended to use a series 70Ω termination resistor on every probe connector (SDI, SDO, MODE, DCLK, PRA and PRB). The 70Ω series termination is used to prevent data transmission corruption ...
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Table 1-3 • Test Access Port Descriptions Port TMS (Test Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK) Select) TCK (Test Clock Input) Dedicated test logic ...
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Automotive FPGA Families JTAG Mode Activation The JTAG test logic circuit is activated in the Designer software by selecting Tools and then Device Selection. This brings up the Device Selection dialog box as shown in Figure 1-14. ...
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Development Tool Support The automotive-grade MX family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the ...
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Automotive FPGA Families 5.0V Operating Conditions Absolute Maximum Ratings Free Air Temperature Range Symbol Parameter Supply Voltage CC CCA CCI V Input Voltage –0 Output Voltage –0 ...
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Power Dissipation General Power Equation standby + I active – CCI OH where: I standby is the current flowing when no inputs or CC ...
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... Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz Fixed Capacitance Values for MX FPGAs (pF) 3.5 6.9 Device Type 18.2 A40MX02 ) 1.4 EQCR A40MX04 A42MX09 A42MX16 A42MX24 * Modules A42MX36 + ...
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Junction Temperature The temperature variable in the Designer software refers to the junction temperature, temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. be used to calculate junction ...
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Automotive FPGA Families Timing Information Input Delay I/O Module t = 1.2 ns INYL Array Clock t = 8.1 ns CKH F = 116 MHz MAX Note: * Values are shown for 40MX at worst-case 5.0V automotive ...
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Input Delays I/O Module t = 1.7 ns INPY 0.0 ns INH t = 0.8 ns INSU t = 2.4 ns INGO Quadrant Clocks t = 4.5 ns† CKH F = 116 MHz MAX Notes: ...
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Automotive FPGA Families Input Delays I/O Module INPY 0.8 ns INSU = 0 INH = 2 INGO Array Clocks F = 123 MHz ...
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Parameter Measurement In 50% 50 1.5V PAD 1. DLH t DHL Figure 1-19 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the output under test Figure 1-20 • AC Test Loads ...
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Automotive FPGA Families Sequential Timing Characteristics PAD INBUF 3V PAD 1.5V 1.5V V CCI Y 50% GND t t INYH INYL Figure 1-21 • Input Buffer Delays SUD G, CLK E Q PRE, CLR ...
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D G Figure 1-25 • Output Buffer Latches CLK Figure 1-24 • Input Buffer Latches D PAD OBDLHS G t OUTSU t OUTH PAD DATA IBDL G PAD DATA G t INSU CLK t SU EXT v3.1 40MX and 42MX ...
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Automotive FPGA Families Decode Module Timing A– Figure 1-26 • Decode Module Timing WRAD [5:0] BLKEN WEN WCLK WD [7:0] Figure 1-27 • SRAM Timing Characteristics 1 -2 ...
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Dual-Port SRAM Timing Waveforms WCLK WD[7:0] WRAD[5:0] WEN BLKEN Note: Identical timing for falling edge clock. Figure 1-28 • 42MX SRAM Write Operation RCLK REN RDAD[5:0] RD[7:0] Note: Identical timing for falling edge clock. Figure 1-29 • 42MX SRAM Synchronous ...
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Automotive FPGA Families RDAD[5:0] RD[7:0] Figure 1-30 • 42MX SRAM Asynchronous Read Operation—Type 1 WEN WD[7:0] WRAD[5:0] BLKEN WCLK RD[7:0] Figure 1-31 • 42MX SRAM Asynchronous Read Operation—Type (Read Address Controlled) t RDADV ...
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Predictable Performance: Tight Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the ...
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Automotive FPGA Families Temperature and Voltage Derating Factors Table 1-7 • 42MX Temperature and Voltage Derating Factors (Normalized 125° CCA CCI 42MX Voltage –55°C –40°C 4.75 0.66 0.67 5.00 0.64 0.65 ...
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Table 1-8 • 40MX Temperature and Voltage Derating Factors (Normalized 125° 4.75V 40MX Voltage –55°C –40°C 4.75 0.62 0.64 5.00 0.60 0.62 5.25 0.58 0.60 40MX Derating Factor (Normalized 125°C, ...
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... Automotive FPGA Families Timing Characteristics The timing numbers in the datasheet represent sample timing characteristics of the devices. Refer to the Timer tool in the Designer software for design-specific timing information. Table 1-9 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Logic Module Propagation Delays ...
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... Table 1-9 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Global Clock Networks t Input Low to HIGH CKH t Input High to LOW CKL t Minimum Pulse Width HIGH PWH t Minimum Pulse Width LOW PWL t Maximum Skew CKSW t Minimum Period P f Maximum Frequency MAX ...
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Automotive FPGA Families Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to-Q GO ...
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Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Global Clock Network t Input Low to HIGH CKH t Input High to LOW CKL t Minimum Pulse Width HIGH PWH t Minimum Pulse Width LOW ...
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Automotive FPGA Families Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter 1 Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) ...
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Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay IRD4 t ...
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Automotive FPGA Families Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter t Enable Pad Z to LOW ENZL t Enable Pad HIGH to Z ENHZ t Enable Pad LOW to Z ...
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Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter 1 Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module Predicted Routing ...
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Automotive FPGA Families Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 ...
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Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter t Enable Pad Z to LOW ENZL t Enable Pad HIGH to Z ENHZ t Enable Pad LOW to Z ENLZ t G-to-Pad HIGH GLH t ...
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Automotive FPGA Families Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing ...
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Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay IRD4 t ...
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Automotive FPGA Families Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH ...
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Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing Delays t FO=1 Routing Delay RD1 ...
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Automotive FPGA Families Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter t Read Enable Set-Up RENSU t Read Enable Hold RENH t Write Enable Set-Up WENSU t Write Enable Hold WENH ...
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Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter Global Clock Network t Input Low to HIGH CKH t Input High to LOW CKL t Minimum Pulse Width HIGH PWH t Minimum Pulse Width LOW ...
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Automotive FPGA Families Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V Parameter t G-to-Pad LOW GHL t I/O Latch Set-Up LSU t I/O Latch Hold LH t I/O Latch Clock-to-Out (Pad-to-Pad), 32 ...
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... Unused I/O pins are configured by the Designer software as shown in Table Table 1-15 • Configuration of Unused I/Os Device A40MX02, A40MX04 A42MX09, A42MX16 A42MX24, A42MX36 In all cases recommended to tie all unused I/O pins to LOW on the board. This applies to all dual-purpose pins when configured as I/Os as well. ...
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Automotive FPGA Families TDO, I/O Test Data Out Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer software. BST pins are only ...
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Package Pin Assignments 68-Pin PLCC Figure 2-1 • 68-Pin PLCC Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 1 68 68-Pin PLCC v3.1 2-1 ...
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... Pin Number I/O 46 I I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 GND 59 GND 60 I/O 61 I/O 62 I/O 63 I I/O 67 I/O 68 I/O V CCy I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O v3.1 68-Pin PLCC A40MX02 Function I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE V CC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O ...
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PLCC Figure 2-2 • 84-Pin PLCC Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 1 84 84-Pin PLCC v3.1 2-3 ...
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Automotive FPGA Families 84-Pin PLCC Pin A40MX04 Number Function 1 I/O 2 I I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I I/O 14 ...
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PQFP 100 1 Figure 2-3 • 100-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 100-Pin PQFP v3.1 2-5 ...
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... I/O 43 GND 44 I/O 45 I/O 46 I/O 47 I/O 48 I CCA V 52 CCI I I/O 55 I/O 56 GND 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 GND 69 I/O 70 v3.1 100-Pin PQFP A40MX02 A40MX04 A42MX09 Function Function Function GND GND I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O V CCA I/O I/O I/O I/O I I/O I/O I/O I/O I/O GND I/O I/O I/O NC I/O I/O NC I/O I/O NC I SDO, I/O ...
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... PQFP A40MX02 A40MX04 Pin Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I I/O 83 I/O I/O 84 I/O I/O 85 I/O I/O 86 GND GND 87 GND GND 88 I/O I/O 89 I/O I/O 90 CLK, I/O CLK, I/O 91 I/O I/O 92 MODE MODE I I I/O 98 SDI, I/O SDI, I/O 99 DCLK, I/O ...
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Automotive FPGA Families 160-Pin PQFP 160 1 Figure 2-4 • Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html 160-Pin PQFP v3.1 ...
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PQFP A42MX09 Pin Number Function 1 I/O 2 DCLK, I I I/O 8 I GND I/O 14 I/O 15 I/O 16 PRB, I/O ...
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Automotive FPGA Families 160-Pin PQFP A42MX09 Pin Number Function 81 I/O 82 SDO, I/O 83 I/O 84 I I/O 88 I/O 89 GND I/O 92 I/O 93 I/O 94 ...
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VQFP Figure 2-5 • 80-Pin VQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 80 1 80-Pin VQFP v3.1 2-11 ...
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... CC I/O 57 I/O 58 I/O 59 I/O 60 I I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 GND 70 I/O 71 I/O 72 I/O 73 I I/O 77 I/O 78 I/O 79 I/O 80 I/O I/O I/O I/O I/O I/O v3.1 80-Pin VQFP A40MX02 A40MX04 Function Function I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O CLK, I/O CLK, I/O I/O I/O MODE MODE I/O NC I/O NC I/O SDI, I/O SDI, I/O DCLK, I/O DCLK, I/O PRA, I/O PRA, I PRB, I/O PRB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O ...
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PQFP 208 1 Figure 2-6 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 208-Pin PQFP v3.1 2-13 ...
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Automotive FPGA Families 208-Pin PQFP A42MX16 A42MX24 Pin Number Function Function 1 GND GND CCA 3 MODE MODE 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 ...
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PQFP A42MX16 A42MX24 Pin Number Function Function 71 I/O WD, I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 GND GND CCA CCA 80 NC ...
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Automotive FPGA Families 208-Pin PQFP A42MX16 A42MX24 Pin Number Function Function 141 NC I/O 142 I/O I/O 143 I/O I/O 144 I/O I/O 145 I/O I/O 146 NC I/O 147 NC I/O 148 NC I/O 149 NC ...
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PQFP 240 1 • • • Figure 2-7 • 240-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 240-Pin PQFP v3.1 • • • 2-17 ...
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Automotive FPGA Families 240-Pin PQFP Pin A42MX36 Number Function 1 I/O 2 DCLK, I/O 3 I/O 4 I/O 5 I/O 6 WD, I/O 7 WD, I CCI 9 I/O 10 I/O 11 I/O 12 I/O ...
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PQFP Pin A42MX36 Number Function 121 GND 122 I/O 123 SDO, TDO, I/O 124 I/O 125 WD, I/O 126 WD, I/O 127 I/O 128 V CCI 129 I/O 130 I/O 131 I/O 132 WD, I/O 133 WD, I/O 134 ...
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Automotive FPGA Families 100-Pin VQFP 100 1 Figure 2-8 • 100-Pin VQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html 100-Pin VQFP v3.1 ...
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VQFP A42MX09 Pin Number Function 1 I/O 2 MODE 3 I/O 4 I/O 5 I/O 6 I/O 7 GND 8 I/O 9 I/O 10 I/O 11 I/O 12 I CCA 15 V CCI 16 I/O ...
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Automotive FPGA Families 100-Pin VQFP A42MX09 Pin Number Function 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 SDI, I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 GND 83 I/O 84 ...
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TQFP 176 1 Figure 2-9 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 40MX and 42MX Automotive FPGA Families 176-Pin TQFP v3.1 2-23 ...
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Automotive FPGA Families 176-Pin TQFP A42MX09 A42MX16 Pin Number Function Function 1 GND GND 2 MODE MODE 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I I/O ...
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TQFP A42MX09 A42MX16 Pin Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I I/O 75 I/O I/O 76 I/O I I/O 79 I/O I I/O 81 I/O ...
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Automotive FPGA Families 176-Pin TQFP A42MX09 A42MX16 Pin Number Function Function 141 I/O I/O 142 I/O I/O 143 NC I/O 144 NC I/O 145 NC NC 146 I/O I/O 147 NC I/O 148 I/O I/O 149 I/O ...
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... The "Pin Descriptions" Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The definition of these categories are as follows: Product Brief The product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information ...
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