SDA5648X SIEMENS [Siemens Semiconductor Group], SDA5648X Datasheet - Page 6

• Manufacturer Part Number: SDA5648X
• Description: Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

I
General Information
The I
reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only
by the bus master usually being a micro controller, whereas the SDA line is controlled either by the
master or by the slave. A data transfer can only be initiated by the bus master when the bus is free,
i.e., both SDA and SCL lines are in a high state. As a general rule for the I
changes state only when the SCL line is low. The only exception to that rule are the Start Condition
and the Stop Condition. Further details are given below. The following abbreviations are used:
START :
AS :
AM :
NAM :
STOP :
Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the
following table
CS0 Input
Low
High
Write Mode
For writing to the PDC decoder, the following format has to be used:
Data Transfer (Write Mode)
Step1 : In order to start a data transfer the master generates a Start Condition on the bus by pulling
Step 2 : The bus master puts the chip address on the SDA line during the next eight SCL pulses.
Step 3 : The master releases the SDA line during the ninth clock pulse. Thus the slave can generate
Step 4 : The controller transmits the data byte to set the Control register.
Step 5 : The slave acknowledges the reception of the byte.
Step 6 : The master concludes the data communication by generating a Stop Condition.
The write mode is used to set the I
Semiconductor Group
2
START
C-Bus
2
C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i.e., both
the SDA line low while the SCL line is held high.
an acknowledge (AS) by pulling the SDA line to a low level.
Chipadress White Mode
Start Condition generated by master
Ackknowledge by slave
Ackknowledge by master
No Ackknowledge by master
Stop Condition generated by master
Write Mode
20 (hex)
22 (hex)
2
C-Bus control register which determines the operating mode:
AS
26
Byte Set Control Register
Read Mode
21 (hex)
23 (hex)
2
C-Bus, the SDA line
AS
SDA 5648X
SDA 5648
STOP