ISL1903EVAL2Z INTERSIL [Intersil Corporation], ISL1903EVAL2Z Datasheet - Page 16

• Manufacturer Part Number: ISL1903EVAL2Z
• Description: Dimmable Buck LED Driver - AC Mains or DC Input LED Driver
• Manufacturer: INTERSIL [Intersil Corporation]

Control Loop
The control loop configuration is user adjustable with the
selection of the external compensation components. For
applications requiring power factor correction (PFC), a very low
bandwidth integrator is used, typically 20Hz or less. In other
applications, the control loop bandwidth can be increased as
required like any other externally compensated voltage mode
PWM controller.
Referring to Figure 11, the FET switching current flowing through
Rs, is applied to the OC pin of the ISL1903. The peak signal is
sampled, buffered, and output on IOUT with a gain of four. The
voltage on IOUT represents 8x the average load current on a
cycle-by-cycle basis. In PFC applications, IOUT tracks the rectified
AC voltage waveform and must be averaged. For DC input
applications, this is obviously not required.
IOUT
where IOUT is the average or DC value of IOUT. Prior to applying
IOUT to the EA at the FB pin it must be scaled such that at
maximum output current the signal is equal to the maximum EA
reference level (nominally 0.530V), while also limiting the
maximum peak primary OC signal to less than the overcurrent
threshold of 0.6V.
R
where I
current limit threshold, and Rs is the current sensing resistor.
Once the value of Rs is determined, Equation 11 can be used to
solve for the maximum level of OC at any steady state current
when Io is substituted for IoCL and solving for Voc.
The EA compensation depends on the bandwidth required for the
application. For PFC applications the BW is necessarily limited to
20Hz or less. For other applications, the BW may be increased as
required up to about 1/5 of the lowest switching frequency
allowed as described in “Oscillator” on page 13. For the low BW
applications a Type I compensation configuration is adequate.
s
=
------------------- -
π I
=
V
oCL
⋅
OC
8 Rs
-------------- - I
R
oCL
N
S
FIGURE 11. CONTROL LOOP CONFIGURATION
LOAD
⋅
sp
is the output current limit threshold, V
R
⋅
PU
o
Ω
VREF
VERR
OUT
OC
AC
V
GENERATOR
REFERENCE
PROCESSOR
OC - IOUT
ISL1903
C
FB
16
+
_
IOUT
FB
R
FB
R1
R2
OC
is the
C
FILTER
(EQ. 10)
(EQ. 11)
ISL1903
For higher BW applications, a Type II configuration may be
required. Figures 11 and 12 show the Type I and Type II
configurations, respectively.
OVP
The ISL1903 has independent overvoltage protection accessed
through the OV pin. There is a nominal 20µA switched current
source used to create hysteresis. The current source is active only
during an OV fault; otherwise, it is inactive and does not affect
the node voltage. The magnitude of the hysteresis voltage is a
function of the external resistor divider impedance.
V
If the divider formed by R1 and R2 is sufficiently high
impedance, R3 is not required, and the hysteresis is:
ΔV
If that does not result in the desired hysteresis then R3 is
needed, and the hysteresis is:
ΔV
If the OV signal requires filtering, the filter capacitor, Copt, should
be placed as shown in Figure 10. The current hysteresis provides
ov ri
(
=
=
sin
20 10
20 10
MONITORED
R
g
VOLTAGE
⋅
⋅
PU
)
=
–
–
FIGURE 12. TYPE II EA CONFIGURATION
1.5
6
6
C
V
V
⋅
⋅
AC
OPT
REF
ERR
R1
⎛
⎝
C
⋅
R1
(
-------------------------- -
FB1
R1
GENERATOR
REFERENCE
FIGURE 13. OV HYSTERESIS
+
ISL1903
R2
R3
+
C
R2
V
FB2
+
_
⋅
(
-------------------------- -
)
R1
R1
R2
R
R2
+
FB2
R3
I
FB
OUT
R2
V
)
⎞
⎠
VREF
1
R
1.5V
FB1
R1
R2
V
0
20µA
+
_
September 20, 2012
C
FILTER
FN8285.1
(EQ. 12)
(EQ. 13)
(EQ. 14)