ls7266r1 LSI Computer Systems, Inc., ls7266r1 Datasheet - Page 2

• Manufacturer Part Number: ls7266r1
• Description: 24-bit Dual-axis Quadrature Counter
• Manufacturer: LSI Computer Systems, Inc.

7266R1-012703-2
Reset and Load Signal Decoders: XRLD and YRLD
Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer
CNTR to OL, reset CNTR, reset FLAG and reset BP
Filter Clock Prescalers: XPSC and YPSC
Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is down loaded
into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate independent filter
clock frequencies for each channel. The PSCs generate the internal filter clock, FCKn used to
validate inputs X
Final filter clock frequency f
mode, f
filter clock is not needed and the FCK input (Pin 2), should be tied to V
Flag Register: XFLAG and YFLAG
The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a
FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the
input filter circuits. E = 1 indicates excessive noise at the inputs but not a definite count error. Once set, E can
only be reset via the RLD.
FCK
n
8f
A
QA
, X
(or 8f
B
, Y
7
A
QB
, Y
6
), where f
B
FCKn
7
5
in the quadrature mode.
6
4
FLAG
= ( f
5
RLD
3
QA
FCK
4
2
and f
3
/(n+1) )
1
2
QB
0
1
,
are the clock frequencies at inputs A and B. In non-quadrature mode
where n = PSC = 0 to FF
0
IDX: Index. Set to 1 when selected index input is at active level.
0
BT: Borrow Toggle flip-flop.
CT: Carry toggle flip-flop.
CPT: Compare toggle flip-flop.
S: Sign flag. Set to1 when CNTR underflows.
E: Error flag. Set to 1 when excessive noise is present at the count
U/D: Up/Down flag. Set to 1 when counting up
.
:
Reset to 0 when CNTR overflows.
inputs in quadrature mode. Irrelevant in non-quadrature mode.
Toggles every time CNTR underflows.
Toggles every time CNTR overflows.
Toggles every time PR equals CNTR.
and reset to 0 when counting down.
Not used. Always reset to 0.
0: NOP
1: Reset BP
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
1
: Select the RLD addressed by X/Y input
: NOP
: Reset CNTR
: Reset BT, CT, CPT,S
: Reset E
: NOP
: Transfer PR to CNTR
: Transfer CNTR to OL
: Transfer PR0 to PSC
: Select RLD
: Select both XRLD and YRLD together
(Note: D7 = 1 overrides X/Y input)
(Note: All 24-bits are transferred in parallel)
(Note: All 24-bits are transferred in parallel)
DD
.
H.
For proper counting in the quadrature