lc72134m Sanyo Semiconductor Corporation, lc72134m Datasheet - Page 13

• Manufacturer Part Number: lc72134m
• Description: Dual Pll Frequency Synthesizer For Fm Tuner Systems
• Manufacturer: Sanyo Semiconductor Corporation

Continued from preceding page.
No.
10
11
12
13
14
15
16
17
Main charge pump
Sub PLL reference
pump control data
Control block/data
Sub PLL charge
detection output
Unlocked state
programmable
switching data
control data
TEST0 to 2
divider data
divider data
PS0 to 12
RS0, RS1
ULa, ULb
Test data
Sub PLL
SDVS
SDLC
DLC
IFS
*
• Controls the charge pump output (PDa).
* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,
• This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in
• Test data
• This bit must be set to 0.
• Specifies the divisor for the sub PLL programmable divider (FMINb).
• The divisor can be set to a value in the range 272 to 8191. Since the internal divide-by-two prescaler is
• Sets the sub PLL programmable divider operating state.
*: See the “Structure of the Programmable Divider” section for details.
• Forcibly controls the charge pump output (PDb).
* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,
• Sub PLL reference frequency (fref) selection data
• The unlocked state information output from the DO pin can be selected to be that for either the main PLL
applications can get out of the deadlocked state by setting the charge pump output to low and setting
Vtune to V
which the sensitivity is reduced by about 10 to 30 mV rms.
All these bits are set to 0 after a power on reset.
This is a binary value in which PS0 is the LSB and PS12 the MSB.
used, the actual divisor will be twice the set value.
applications can get out of the deadlocked state by setting the charge pump output to low and setting
Vtune to V
or the sub PLL.
SDVS
SDLC
TEST0
TEST1
TEST2
DLC
RS1
ULb
0
1
1
0
0
1
0
0
1
1
0
0
1
1
CC
CC
Charge pump output
Charge pump output
. (Deadlock clear circuit)
. (Deadlock clear circuit)
All these bits must be set to 0.
The FMINb counter is stopped
Normal operation
Normal operation
RS0
ULa
The FMINb counter operates
0
1
0
1
0
1
0
1
Forced to low
Forced to low
(FMINb is pulled down)
Operating state
No unlocked state information is output. The output data, UL is 1.
Main PLL unlocked state information
Sub PLL unlocked state information
Main PLL plus sub PLL unlocked state information.
(Indicates that either the main or the sub PLL is unlocked.)
Reference frequency
50
25
12.5
15
kHz
LC72134M
Unlocked state information
Function
Input pin frequency range
10 to 160 MHz
Related data
No. 5814-13/27