SST49LF004B-33-4C-WHE SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-WHE Datasheet
SST49LF004B-33-4C-WHE
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SST49LF004B-33-4C-WHE Summary of contents
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... The SST49LF004B devices write (Program or Erase) with a single 3.0-3.6V power supply. The SST49LF004B use less energy during Erase and Pro- gram than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, cur- rent and time of application ...
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... Silicon Storage Technology, Inc. 4 Mbit Firmware Hub To meet high density, surface mount requirements, the SST49LF004B is offered in both 32-lead PLCC and 32- lead TSOP packages. In addition, SST provides lead-free (non-Pb) package options to address the growing need for non-Pb solutions in electronic components. Non-Pb pack- age version can be obtained by ordering products with a package code suffix of “ ...
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... Mbit Firmware Hub SST49LF004B LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Firmware Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Firmware Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Response to Invalid Fields for Firmware Memory Cycle Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Registers PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Protection (PP Mode) ...
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... FIGURE 17: Block-Erase Timing Diagram (PP Mode FIGURE 18: Chip-Erase Timing Diagram (PP Mode FIGURE 19: Software ID Entry and Read (PP Mode FIGURE 20: Software ID Exit (PP Mode FIGURE 21: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 22: A Test Load Example ©2006 Silicon Storage Technology, Inc. 4 Mbit Firmware Hub 4 SST49LF004B S71307-02-000 2/06 ...
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... Mbit Firmware Hub SST49LF004B LIST OF TABLES TABLE 1: Pin Description TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3: Firmware Memory Cycles START Field Definition TABLE 4: Firmware Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 5: Firmware Memory Write Cycle TABLE 6: Firmware Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 7: Block Locking Registers TABLE 8: Block Locking Register Bits ...
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... IAGRAM TBL# WP# INIT# LAD[3:0] LCLK LPC LFRAME# Interface ID[3:0] GPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# ©2006 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic MODE RST Mbit Firmware Hub SST49LF004B SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1307 B1.0 S71307-02-000 2/06 ...
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... Mbit Firmware Hub SST49LF004B PIN ASSIGNMENTS A7(GPI1) A6 (GPI0) A5 (WP#) A4 (TBL#) A3 (ID3) A2 (ID2) A1 (ID1) A0 (ID0) DQ0 (LAD0 Designates LPC Mode FIGURE SSIGNMENTS FOR MODE (MODE) A10 (FGPI4) R/C# (CLK RST# (RST#) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) ...
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... To gate the data output buffers control the Write operations. X These pins must be left unconnected provide power supply (3.0-3.6V Circuit ground (0V reference) N/A N/A Unconnected pins Mbit Firmware Hub SST49LF004B ) for PP mode and low (V ) for LPC mode. This IH IL T1.2 1307 S71307-02-000 2/06 ...
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... Write Protect / Top Block Lock The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device mem- ory in the SST49LF004B. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest memory address range for the SST49LF004B. The WP# pin write protects the remaining sectors in the flash memory ...
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... Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system. 2. The device ID for SST49LF004B is the same as SST49LF004A Mbit Firmware Hub SST49LF004B ...
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... Interface Specification. The host drives LFRAME# low for one or more clock cycles to initiate an LPC cycle. The last latched value of LAD[3:0] before LFRAME# is the START value. The START value determines whether the SST49LF004B will respond to a Firmware Memory Read or Firmware Memory Write cycle as defined in Table 3. TABLE 3: F IRMWARE ...
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... A[7:4] A[3: EAD YCLE AVEFORM 12 4 Mbit Firmware Hub SST49LF004B SST49LF004B device should respond. If the SST49LF004B takes control of the bus during this SST49LF004B drives the bus to all MSIZE TAR0 TAR1 RSYNC DATA 0000b 1111b Tri-State 0000b D[3:0] D[7:4] TAR 1307 F03.0 S71307-02-000 T4 ...
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... The host resumes control of the bus during this cycle. MADDR A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3: RITE YCLE AVEFORM 13 Preliminary Specifications SST49LF004B device should takes control of the bus during this SST49LF004B drives the bus to MSIZE DATA TAR0 TAR1 RSYNC 0000b D[7:4] 1111b Tri-State 0000b TAR D[3:0] 1307 F04.0 S71307-02-000 T5.0 1307 2/06 ...
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... For Firmware Memory Read/Write cycles, hardware strap- ping values on ID[3:0] must match the values in IDSEL field. See Table 6 for multiple device selection configura- tions. The SST49LF004B will compare the IDSEL field with ID[3:0]'s strapping values. If there is a mismatch, the device will ignore the reminder of the cycle. ...
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... If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling When the SST49LF004B device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data ...
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... B ITS Write-Lock Bit [ Mbit Firmware Hub SST49LF004B Memory Map Register Address FFBF0002H FFBE0002H FFBD0002H FFBC0002H FFBB0002H FFBA0002H FFB90002H FFB80002H T7.0 1307 Lock Status Full Access Write Locked (Default State at Power-Up) Locked Open (Full Access Locked Down) Write Locked Down T8 ...
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... R/C# and the column address is latched on the rising edge of R/C#. Read The Read operation of the SST49LF004B device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 11, for further details. ...
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... Device ID = 60H for SST49LF004B Data# Polling DQ 7 When the SST49LF004B device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data. Once the Program operation is completed, DQ will produce true data. Note that even ...
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... Mbit Firmware Hub SST49LF004B SOFTWARE COMMAND SEQUENCE TABLE 10 OFTWARE OMMAND 1 1st Cycle Command Sequence 2 Addr Data Addr Byte-Program YYYY 5555H AAH YYYY 2AAAH Sector-Erase YYYY 5555H AAH YYYY 2AAAH Block-Erase YYYY 5555H AAH YYYY 2AAAH 6 Chip-Erase YYYY 5555H AAH YYYY 2AAAH ...
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... C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest information 3.0-3. Mbit Firmware Hub SST49LF004B +0. +2. S71307-02-000 2/06 ...
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... Mbit Firmware Hub SST49LF004B DC Characteristics TABLE 11 PERATING HARACTERISTICS Symbol Parameter 1 I Active V Current DD DD Read 2 Write I Standby V Current SB DD (LPC Interface Input Current for Mode RY and ID[3:0] pins I Input Leakage Current for I Mode and ID[3:0] pins I Input Leakage Current LI I Output Leakage Current ...
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... Silicon Storage Technology, Inc. Minimum Specification 10,000 100 100 + I DD (LPC M ) ODE T cyc T high 0 (LPC M ) ODE 22 4 Mbit Firmware Hub SST49LF004B Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Min Max low 0.4 V ...
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... Mbit Firmware Hub SST49LF004B AC Characteristics (LPC Mode) TABLE 16 EAD RITE YCLE Symbol Parameter T Clock Cycle Time CYC T Data Set Up Time to Clock Rising SU T Clock Rising to Data Hold Time Clock Rising to Data Valid VAL T Byte Programming Time BP T Sector-Erase Time ...
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... T P NPUT IMING ARAMETERS ©2006 Silicon Storage Technology, Inc. V LCLK TEST T VAL LAD [3:0] LAD [3: OFF (LPC M ) ODE T SU Inputs Valid (LPC M ) ODE 24 4 Mbit Firmware Hub SST49LF004B 1307 F06 TEST MAX 1307 F07.0 S71307-02-000 2/06 ...
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... Mbit Firmware Hub SST49LF004B TABLE 18 NTERFACE EASUREMENT Symbol TEST 1 V MAX Input Signal Edge Rate 1. The input test environment is done with 0.1 V drive than this. V specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use MAX different voltage values, but must correlate results back to these parameters ...
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... Silicon Storage Technology, Inc =3.0-3.6V ( ODE reset procedure is performed during a programming or erase operational. RSTC T PRST T RSTP T RSTF ( ODE 26 4 Mbit Firmware Hub SST49LF004B Min Max Units 1 ms 100 µs 10 µs 50 µs Row Address Sector-/Block-Erase ...
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... Mbit Firmware Hub SST49LF004B AC Characteristics (PP Mode) TABLE 21 EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T RST# High to Row Address Setup RST T R/C# Address Set-up Time AS T R/C# Address Hold Time AH T Address Access Time AA T Output Enable Access Time OE T OE# Low to Active Output ...
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... OLZ D ( IAGRAM ODE Column Address CWH T OES Data Valid D ( IAGRAM ODE 28 4 Mbit Firmware Hub SST49LF004B Row Address Column Address OHZ High-Z Data Valid 1307 F10.0 T OEH T WPH DH 1307 F11.0 S71307-02-000 2/06 ...
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... Mbit Firmware Hub SST49LF004B Row Addresses R/C# WE# OE FIGURE 13 ATA OLLING IMING Row Column Addresses R/C# WE# OE FIGURE 14 OGGLE IT IMING ©2006 Silicon Storage Technology, Inc. Column T OEP IAGRAM ODE T OET D ( IAGRAM ODE 29 Preliminary Specifications ...
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... Silicon Storage Technology, Inc. 2AAA 5555 ( IAGRAM ODE 2AAA 5555 5555 ( IAGRAM ODE 30 4 Mbit Firmware Hub SST49LF004B Internal Program Starts DATA 1307 F14.0 2AAA SA X Internal Erase Starts 55 30 1307 F15.0 S71307-02-000 2/06 ...
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... Mbit Firmware Hub SST49LF004B A 14-0 5555 R/C# OE Block Address X FIGURE 17 LOCK RASE IMING A 14-0 5555 R/C# OE# WE 7-0 FIGURE 18 HIP RASE IMING ©2006 Silicon Storage Technology, Inc. 2AAA 5555 5555 ( IAGRAM ODE 2AAA 5555 5555 (PP M ...
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... OFTWARE NTRY AND A 14-0 5555 R/C# OE# WE# DQ 7-0 FIGURE 20 OFTWARE XIT ©2006 Silicon Storage Technology, Inc. Software ID Entry 5555 T IDA 55 90 Device ID = 60H for SST49LF004B R ( EAD ODE 2AAA 5555 ODE 32 4 Mbit Firmware Hub SST49LF004B 0000 0001 T AA Device ID BF 1307 F18 ...
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... Mbit Firmware Hub SST49LF004B V IHT INPUT V ILT AC test inputs are driven at V (0.9 IHT points for inputs and outputs are V FIGURE 21 NPUT UTPUT TO DUT FIGURE 22 EST OAD XAMPLE ©2006 Silicon Storage Technology, Inc REFERENCE POINTS ) for a logic “1” and V (0 ...
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... SST49LF004B - XXX - XX Valid combinations for SST49LF004B SST49LF004B-33-4C-NHE SST49LF004B-33-4C-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. ...
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... Mbit Firmware Hub SST49LF004B PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2006 Silicon Storage Technology, Inc. 8.10 7.90 1.20 max. (TSOP ACKAGE Description www.SuperFlash.com or www.sst.com 36 4 Mbit Firmware Hub SST49LF004B 1.05 0.95 0.50 BSC 0.27 0.17 0.15 0.05 DETAIL 0˚- 5˚ 0.70 0.50 32-tsop-WH-7 1mm ...