AD668 AD [Analog Devices], AD668 Datasheet - Page 15

• Manufacturer Part Number: AD668
• Description: 12-Bit Ultrahigh Speed Multiplying D/A Converter
• Manufacturer: AD [Analog Devices]

16
REV. A
bringing a latch clock pulse on board, whose opposite edge in-
evitably produces a substantial glitch, even when the DAC is not
supposed to be changing codes.
Data Skew
The AD668, like many of its slower predecessors, essentially
uses each digital input line to switch a separate, weighted cur-
rent to either the output (I
COM). If the input bits are not changed simultaneously, or if
the different DAC bits switch at different speeds, then the DAC
output current will momentarily take on some incorrect value.
This effect is particularly troublesome at the “carry points,”
where the DAC output is to change by only one LSB, but sev-
eral of the larger current sources must be switched to realize this
change. Data skew can allow the DAC output to move a sub-
stantial amount towards full scale or zero (depending upon the
direction of the skew) when only a small transition is desired.
Great care was taken in the design and layout of the AD668 to
ensure that switching times of the DAC switches are symmetri-
cal and that the length of the input data lines are short and well
matched. The glitch-sensitive user should be equally diligent
about minimizing the data skew at the AD668’s inputs, particu-
larly for the 4 or 5 most significant bits. This can be achieved by
using the proper logic family and gate to drive the DAC, and
keeping the interconnect lines between the log outputs and the
DAC inputs as short and as well matched as possible, particu-
larly for the most significant bits. The top 6 bits should be
driven from the same latch chip if latches are used.
DEGLITCHING FOR PRECISION WAVEFORM
GENERATION
There are high speed SHAs available with specifications suffi-
+
10124
5V
9
MC
–
C1
0.039 F
8
5V
2
4
TO PIN 2
SD5000
249
R6
–
5V
R7
169
360
R4
OUT
INPUT
MPS 571
–
+
15V
(2)
15V
) or some other node (ANALOG
R8
510
R5
360
D1
IN4735
169
R9
–
5V
100
R1
R10
249
14
16
13
3
6
11
4
8
5
1
12
9
4
5
–15–
AD841
C
100pF
360pF
C
100
R2
HOLD
FILT
cient to deglitch the AD668, however most are hybrid in design
at costs which can be prohibitive. A high performance, low cost
alternative shown in Figure 27 is a discrete SHA utilizing a high
speed monolithic op amp and high speed DMOS FET switches.
This SHA circuit uses the inverting integrator architecture. The
AD841 operational amplifier used (300 MHz gain bandwidth
product) is fabricated on the same high speed process as the
AD668. The time constant formed by the 100
100 pF capacitor determines the acquisition time and also band
limits the output signal to eliminate slew induced distortion.
A discrete drive circuit is used to achieve the best performance
from the SD5000 quad DMOS switch. This switch driving cell
is composed of MPS571 RF npn transistors and an MC10124
TTL to ECL translator. Using this technique provides both
high speed and highly symmetrical drive signals for the SD5000
switches. The switches are arranged in a single-throw double-
pole (SPDT) configuration. The 360 pF “flyback” capacitor is
switched to the op amp summing junction during the hold mode
to keep switching transients from feeding to the output. This
capacitor is grounded during sample mode to minimize its effect
on acquisition time.
Circuit layout for a high speed deglitcher is almost as critical as
the design itself. Figure 28 shows the recommended layout of
the deglitching cell for a double-sided printed circuit board. The
layout is very compact with care taken that all critical signal
paths are short.
Performance of the AD668 in waveform generation applications
is greatly improved with the use of this deglitching method. Peak
harmonics and spurious free dynamic range are typically main-
tained at -70 dB to -75 dB with update rates up to 10 MHz.
10
R3
100
OUTPUT
resistor and the