AD668 AD [Analog Devices], AD668 Datasheet - Page 7

• Manufacturer Part Number: AD668
• Description: 12-Bit Ultrahigh Speed Multiplying D/A Converter
• Manufacturer: AD [Analog Devices]

REV. A
DIGITAL INPUT CONSIDERATIONS
The AD668 uses a standard positive true straight binary code
for unipolar outputs (all 1s full-scale output), and an offset bi-
nary code for bipolar output ranges. In the bipolar mode, with
all 0s on the inputs, the output will go to negative full scale;
with 111 . . . 11, the output will go to positive full scale less
1 LSB; and with 100 . . . 00 (only the MSB on), the output will
go to zero.
The threshold of the digital inputs is set at 1.4 V and does not
vary with supply voltage. This reference is provided by a band-
gap generator, which requires approximately 3 mA of bias
current achieved by tying R
(see Figure 6). The digital bit inputs operate with small input
currents to easily interface to unbuffered CMOS logic. The digi-
tal input signals to the DAC should be isolated from the analog
input and output as much as possible. To minimize undershoot,
ringing, and digital feedthrough noise, the interconnect distance
to the DAC inputs should be kept as short as possible. Termina-
tion resistors may improve performance if the digital lines be-
come too long. The digital inputs should be free from large
glitches and ringing and have 10% to 90% rise and fall times on
the order of 5 ns.
To realize the AD668’s specified ac performance, it is recom-
mended that high speed logic families such as Schottky TTL,
high speed CMOS, or the new lines of high speed TTL be used
exclusively. Table I shows how DAC performance, particularly
glitch, can vary depending on the driving logic used. As this
table indicates, STTL, HCMOS, and FAST* represent the
most viable families for driving the AD668.
Logic
Family
TTL
LSTTL
STTL
HCMOS 12 ns
FAST*
NOTES
1
2
3
4
*FAST is a registered trademark of National Semiconductor Corporation.
All values typical, taken in test fixture diagrammed in Figure 23.
Measurements are made for a 1 V full-scale step into 100
Settling time is measured from the time the digital input crosses the threshold
The worst case glitch impulse, measured on the major carry. DAC full scale is1 V.
voltage (1.4 V) to when the output is within the specified range of its final value.
1
10%-90%
DAC Rise
Time
10.5 ns
11.25 ns
11 ns
11.5 ns
Table I. DAC Performance vs. Drive Logic
R
Figure 6. Equivalent Digital Input
TH
2
1%
47 ns 77 ns 100 ns
35 ns 60 ns 120 ns
50 ns 75 ns 110 ns
53 ns 78 ns 100 ns
49 ns 73 ns 100 ns
V
Settling Time
LOGIC
TH
0.1% (0.025%)
3 mA
to any +V
– 1.4 V
1 LSB
2, 3
LOGIC
Glitch
Impulse Excursion
2.5 nV-s 280 mV
1.2 nV-s 270 mV
500 pV-s 200 mV
350 pV-s 200 mV
2 nV-s
supply where:
DAC load resistance.
4
Maximum
Glitch
250 mV
–7–
The variations in DAC settling and rise times can be attributed
to differences in rise time and current driving capabilities of the
various families. Differences in the glitch impulse are predomi-
nantly dependent upon the variation in data skew. Variations in
these specs occur not only between logic families, but also be-
tween different gates and latches within the same family. When
selecting a gate to drive the AD668 logic input, pay particular
attention to the propagation delay time specs: t
Selecting the smallest delays possible will help to minimize the
settling time, while selection of gates where t
closely matched to one another will minimize the glitch impulse
resulting from data skew. Of the common latches, the 74374
octal flip-flop provides the best performance in this area for
many of the logic families mentioned above.
PIN BY PIN CURRENT ACCOUNTING
The internal wiring and pinout of the AD668 are dictated in
large part by current management constraints. When using low
impedance, high current, high accuracy parts such as the
AD668, great care must be taken in the routing of not only sig-
nal lines, but ground and supply lines as well. The following ac-
counting provides a detailed description of the magnitudes and
signal dependencies of the currents associated with each of the
part’s pins. These descriptions are consistent with the functional
block diagram as well as the equivalent circuits provided in Fig-
ures 4, 5, and 6.
V
the DAC current sources and generally runs about 2.2 times the
DAC’s nominal full scale. By design, this current is independent
of the digital input code but is linearly dependent on analog in-
put variations.
REFCOM – this node provides the reference ground for the
reference amplifier’s current feedback loop (as illustrated in Fig-
ure 5) as well as providing the negative supply voltage for most
of the reference amplifier. The current consists of 1.2 mA of
analog input dependent current and another 3 mA of input in-
dependent current. Analog input voltages should always be pro-
duced with respect to this voltage.
REFIN1 – has a 1k series resistance to the reference amplifier
input and a 5k series resistance to REFIN2. REFIN1 may be
used in conjunction with REFIN2 to provide a 5:1 voltage di-
vider, or the two may be driven in parallel to provide a high
impedance input node (see Figure 5).
REFIN2 – the 4k side of the input resistive divider. Note also
that the combined impedance of these two resistors matches the
effective impedance at the other input of the reference amplifier,
thereby minimizing the offset due to bias currents. Circuits
which alter this effective impedance may suffer increased analog
offset and drift performance degradation as a result of the mis-
match in these impedances.
I
node tied to a virtual ground, a 10.24 mA nominal full scale
output current will flow from this pin. In the voltage output
mode, with R
out of R
resistive loading will cause current to be divided between
LCOM, R
OUT
CC
– the current into this pin is drawn predominantly through
– the output current. In the current output mode with this
L
and the other half will flow out of LCOM. External
L
, and I
L
grounded, half of the output current will flow
OUT
as Figure 4 suggests.
PLH
PLH
and t
AD668
and t
PHL
PHL
are
.