cxd1196ar Sony Electronics, cxd1196ar Datasheet - Page 18

• Manufacturer Part Number: cxd1196ar
• Description: Cd-rom Decoder
• Manufacturer: Sony Electronics

2.1.3
Bit7-5
Bit4
Bit3
Bit2 SWOPN (Sync Window Open)
Bit1
Bit0
Chip Control (CHPCTL) register
(Note 1)
CHPRST (Chip Reset)
When this bit is set at ‘H’, the CXD1196AR is internally initialized. The bit setting will automatically
change to ‘L’ when the internal initialization of the CXD1196AR is completed. Therefore, there is no
need for the CPU to change the setting at ‘L’. Initialization of the CXD1196AR will be completed in
500ns after the bit has been set at ‘H’ by the CPU.
CD-DA (CD-Digital Audio)
‘H’
‘L’
‘H’
‘L’
RPSTART (Repeat Correction Start)
When the DECODER is placed in the repeat correction mode, and this bit set at ‘H’, the error
correction of the current sector will begin. The bit setting will automatically change to ‘L’ when
correction begins. Therefore, there is no need for the CPU to change the setting at ‘L’.
ADPEN (ADPCM Enable)
When the current sector is an ADPCM sector, the CPU sets this bit at ‘H’ in less than 11.5 ms after a
decoder interrupt (DECINT). When the current sector is not an ADPCM sector, the CPU changes the
bit setting at ‘L’ in less than 11.5 ms after a decoder interrupt (DECINT).
RESERVED
:
:
:
:
Sony DSP for CD
(48-bit slot mode)
(64-bit slot mode)
When a CD-DA disc is to be played back, this bit is set at ‘H’.
The decoder must be placed in the disabled state (DECCTL register) when this bit is set at
‘H’.
When a CD-ROM disc is to be played back, this bit is set at ‘L’.
When this bit is set at ‘H’, the window for detection of SYNC mark will open. In this case,
the SYNC protection circuit in the CXD1196AR will be disabled.
When this bit is set at ‘L’, the window for detection of SYNC mark will be controlled by the
SYNC protection circuit in the CXD1196AR.
CDL30 series
CDL35 series
CDL40 series
CDL40 series
CDL30 series
CDL35 series
CDL40 series
Table 2.1.1 DRVIF Register Settings
CXD1125Q/QZ, CXD1130Q/QZ, CXD1135Q/QZ,
CXD1241Q/QZ, CXD1245Q, CXD1246Q/QZ,
CXD1247Q/QZ/R, etc.
CXD1165Q, CXD1167Q/QZ/R, etc.
CXD2500Q/QZ, etc.
bit6
L
L
L
bit5
H
L
L
—18—
DRVIF register
bit4
H
L
L
bit3
H
L
L
bit2
H
H
X
bit1
H
L
L
Fig. 2.1.1 (1)
Fig. 2.1.1 (2)
Fig. 2.1.1 (3)
Timing chart
CXD1196AR