hm51w16165tt-7 Elpida Memory, Inc., hm51w16165tt-7 Datasheet - Page 16

• Manufacturer Part Number: hm51w16165tt-7
• Description: 16 M Edo Dram 1-mword ? 16-bit
• Manufacturer: Elpida Memory, Inc.

HM51W16165 Series, HM51W18165 Series
16
21. t
22. t
23. t
24. t
25. t
26. When output buffers are enabled once, sustain the low impedance state until valid data is
27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
28. Please do not use t
29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024
31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
32. XXX: H or L (H: V
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (t
than the specified t
shown in EDO page mode mix cycle (1) and (2).
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t
transition state from normal operation mode to self refresh mode. If t
precharge time should use t
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
cycles (4096 cycles: HM51W16165 Series, 1024 cycles: HM51W18165 Series) of distributed
CBR refresh with 15.6 µs interval should be executed within 64 or 16 ms (64 ms: HM51W16165,
16 ms: HM51W18165) immediately after exiting from and before entering into the self refresh
mode.
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
ASC
CRP
CWL
CP
HPC
is determined by the time that both UCAS and LCAS are high.
, t
, t
, t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode
CAH
CHR
DH
, t
CC
, t
, t
/V
DS
RCS
RCH
SS
and t
IH
, t
, t
line noise, which causes to degrade V
or V
WCS
CPA
CHS
, t
and t
IH
IL
HPC
RASS
.
WCH
OHR
should be satisfied by both UCAS and LCAS.
(min)
(min) value.The value of CAS cycle time of mixed EDO page mode is
, t
and t
CPW
timing, 10 µs
Data Sheet E0153H10
CSR
are determined by the later rising edge of UCAS or LCAS.
RPS
V
and t
OH
IN
, and between t
instead of t
V
RPC
IH
(max), L: V
are determined by the earlier falling edge of UCAS or LCAS.
t
RASS
RP
.
100 µs. During this period, the device is in
OFR
IL
(min)
and t
IH
min/V
OFF
V
.
IN
IL
max level.
CAS
V
IL
+ t
(max))
CP
RASS
+ 2 t
T
) becomes greater
100 µs, then RAS