SL2101C ZARLINK [Zarlink Semiconductor Inc], SL2101C Datasheet - Page 4

• Manufacturer Part Number: SL2101C
• Description: Synthesized Broadband Converter with Programmable Power
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

SL2101
Data Sheet
Converter Section
In normal application the RF input is interfaced through appropriate impedance matching and an AGC front end to
the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region
of 50 to 1400 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite
distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the
mixer section and back isolation from the local oscillator section.
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The lna/mixer current and hence signal handling and device power consumption are programmable through the I
C
bus as tabulated in Figure 7.
The typical RF input impedance and matching network for broadband upconversion are contained in Figures 8 and
9 respectively and for narrow band downconversion in Figures 10 and 11 respectively. The input referred two tone
intermodulation test condition spectrum at maximum power setting is shown in Figure 12. The typical input NF and
gain versus frequency and NF specification limits, over selectable power settings are contained in Figures 13, 14
and 15 respectively.
The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this
stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The
oscillator block uses an external tuneable network and is optimized for low phase noise. The typical oscillator
application as an upconverter is shown in Figure 16 and the typical phase noise performance in Figure 17. The
typical oscillator application as a downconverter is shown in Figure 18, and the phase noise performance in Figure
19. This oscillator block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator.
Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of
an IF in the range 30-1400 MHz so covering standard HIIFs between 1 and 1.4 GHz and all conventional tuner
output IFs. When used as a broadband upconverter to a HIIF the output should be differentially loaded, for example
with a differential SAW filter, to maximize intermodulation performance. A nominal load in maximum power setting is
shown in Figure 4, which will typically be terminated with a differential 200 load. When used as a narrowband
downconverter the output should be differentially loaded with a discrete differential to single ended converter as in
Figure 5, shown tuned to 44 MHz IF. Alternatively loading can be direct into a differential input amplifier or SAWF, in
which case external loads to Vcc will be required. An example load for 44 MHz application with a gain of 16 dB is
contained in Figure 6. The NF and gain with recommended load versus power setting are contained in Figure 20.
The typical IF output impedance as upconverter and downconverter are contained in Figures 21 and 22
respectively.
In all applications care should be taken to achieve symmetric balance to the IF outputs to maximize intermodulation
performance.
The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section 'Quick Reference
Data'.
PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference
frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance.
The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The
programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
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