em78p131a ELAN Microelectronics Corp, em78p131a Datasheet - Page 17

• Manufacturer Part Number: em78p131a
• Description: 8-bit Microcontroller With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.2) 09.16.2009
(This specification is subject to change without further notice)
5.3 TCC/WDT and Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is
available for the TCC only or WDT only, one at a time and the PAB bit of the CONT
register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the ratio. The prescaler is cleared each time an instruction is written to TCC
in TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by
the “WDTC” or “SLEP” instructions. If the prescaler is earlier assigned to TCC and later
assigned to WDT, or vice versa, the contents of the prescaler counter would be cleared
automatically. Figure 5-4 depicts the circuit diagram of TCC/WDT.
5.4 I/O Ports
The I/O registers, Port 6, are bidirectional tri-state I/O ports. Port 6 can be pulled-high
internally by software except P63. In addition, Port 6 can also have open-drain output
by software except P63. Input status changed interrupt (or wake-up) function is
available from Port 6. P60 ~ P62 pins can be pulled-down by software. Each I/O pin
can be defined as "input" or "output" pin by the I/O control register (IOC6) except P63.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 6 are shown in Figures 5-5, 5-6 and 5-7 respectively.
1
Note: Vdd = 5V, set up time period = 16.5ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
external clock input (edge selectable from TCC pin). If the TCC signal source is
from an internal clock, TCC will increase by 1 at every instruction cycle (without
prescaler). Referring to Figure 5-4, CLK=Fosc/2 or CLK=Fosc/4, depends on the
Code Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is
used if CLK bit is "1". If the TCC signal source is from an external clock input, TCC
is incremented by 1 at every falling edge or rising edge of the TCC pin.
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause
the device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of the IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep
8-Bit Microcontroller with OTP ROM
1
(default).
EM78P131A
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