cxd2589q Sony Electronics, cxd2589q Datasheet - Page 27

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cxd2589q

Manufacturer Part Number
cxd2589q
Description
Cd Digital Signal Processor
Manufacturer
Sony Electronics
Datasheet

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Note) • Values in parentheses are for when DSPB is 1.
$DX commands
CLV CTRL
Command
VP0 to 7 = F0 (H)
VP0 to 7 = E0 (H)
Command bit
Command bit
• Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.
• VP0 to 7 setting values are valid in CAV-W mode.
TB = 0
TB = 1
TP = 0
TP = 1
:
D3
0
1.5
0.5
2
1
Bottom hold at a cycle of RFCK/32 in CLVS mode.
Bottom hold at a cycle of RFCK/16 in CLVS mode.
Peak hold at a cycle of RFCK/4 in CLVS mode.
Peak hold at a cycle of RFCK/2 in CLVS mode.
Playback at half (normal) speed
Playback at normal (double)
speed
D2
TB
Data 1
D1
TP
Description
to
CLVS
Gain
D0
VP0 to 7 setting value [HEX]
VP7
D3
See the $CX commands.
Fig. 1-1
– 27 –
F0
VP6
D2
Data 2
The rotational velocity R of the spindle can be
expressed with the following equation.
Description
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
VP5
D1
R =
VP4
256 – n
D0
32
VP3
D3
E0
VP2
D2
Data 3
VP1
D1
CXD2589Q
VP0
D0

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