k9f2808u0b-ycb0 Samsung Semiconductor, Inc., k9f2808u0b-ycb0 Datasheet
k9f2808u0b-ycb0
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k9f2808u0b-ycb0 Summary of contents
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Document Title 16M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 K9F2808U0B(3.3V device)’s qualification is finished 0.2 K9F2808Q0B (1.8V device) - Changed typical read operation current (Icc1) from 8mA to 5mA - Changed typical program operation current (Icc2) from 8mA to 5mA ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Revision History Revision No. History 0 (R/B) of 1.8V device is changed. OL -min. Value: 7mA -->3mA -typ. Value: 8mA -->4mA 2. AC parameter is changed. tRP(min.) : 30ns --> 25ns 0.5 1. Parameters are changed in 1.8V part(K9F2808Q0B tCH is changed from 15ns to 20ns - tCLH is changed from 15ns to 20ns - tALH is changed from 15ns to 20ns - tDH is changed from 15ns to 20ns 0 ...
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... Program/Erase Lockout During Power Transitions Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years Command Register Operation Package - K9F2808U0B-YCB0/YIB0 : 48 - Pin TSOP I ( 0.5 mm pitch) - K9F2808X0B-DCB 0/ DIB0 63- Ball TBGA ( /0.8mm pitch , Width 1.0 mm) - K9F2808U0B-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm) * K9F2808U0B-V(WSOPI ) is the same device as K9F2808U0B-Y(TSOP1) except package type ...
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... N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡ Æ 0~8 0.45~0.75 0.018~0.030 K9F2808U0B-YCB0/YIB0 20.00 0.20 0.787 0.008 #48 #25 18 ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN CONFIGURATION (TBGA DNU DNU PACKAGE DIMENSIONS 63-Ball TBGA (measured in millimeters) Top View 9.00 0.10 #A1 K9F2808X0B-DCB0/DIB0 DNU DNU DNU DNU /WP ALE NC /CE /WE R/B NC /RE CLE ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN CONFIGURATION (WSOP1) N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2. ARRAY ORGANIZATION 32K Pages 1st half Page Register ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PRODUCT INTRODUCTION The K9F2808X0B is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected like NAND structure ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F2808X0B-YCB0,DCB0 Temperature Under Bias K9F2808X0B-YIB0,DIB 0 Storage Temperature NOTE: 1. Minimum DC voltage is -0.6V on input/output pins and -0.2V on Vcc and VccQ pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 VALID BLOCK Parameter Symbol Valid Block Number NOTE: K9F2808X0B 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits program factory-marked bad blocks ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 AC Timing Characteristics for Command / Address / Data Input Parameter Symbol CLE Set-up Time t CLS CLE Hold Time t CLH CE Setup Time Hold Time Pulse Width t WP ALE Setup Time t ALS ALE Hold Time t ALH Data Setup Time ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding invalid block( called as the invalid block information. Devices ,regardless of having invalid block(s), have the same quality level because all valid blocks have same AC and DC characteristics. An invalid block(s) does not affect the perfor- mance of valid block(s) because it’ ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Pointer Operation of K9F2808X0B Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant saving in power consumption ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 * Command Latch Cycle CLE ALS ALE I Address Latch Cycle t CLS CLE ALS ALE I CLH CLS ALH Command ALH ALS ALH ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 * Input Data Latch Cycle CLE ALS ALE I/O ~ DIN Serial Access Cycle after Read I R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 * Status Read Cycle CLE t CLS I READ1 OPERATION (READ ONE PAGE) CLE ALE 00h or 01h I Column Page(Row) Address Address R/B NOTE : 1) is only valid on K9F2808U0B_Y or K9F2808U0B_V t CLR t CLH t CH ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/O ~ 50h R/B M Address PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Page(Row) Input Command Address Address R ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE I/O ~ 60h Page(Row) Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I 90h Address. 1cycle Read ID Command ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the fol- lowing page read operation ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(3Cycle) I & Don t Care) Figure 7-1. Sequential Row Read1 Operation (only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block) R/B I 00h Start Add.(3Cycle) ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Figure 8-1. Sequential Row Read2 Operation (GND Input=Fixed Low) (only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block) R/B I/O ~ Start Add.(3Cycle 50h & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up to 528 single page program cycle ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 BLOCK ERASE The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2 cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This two- step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condition ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command register remains in Read ID mode until further commands are issued to it. ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 READY/BUSY The device has output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Data Protection & Powerup sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V/2V(K9F2808Q0B:1.1V, K9F2808U0B:2V). WP pin provides hardware pro- tection and is recommended to be kept at V before internal circuit gets ready for any command sequences as shown in Figure 14 ...