hy5du573222afm Hynix Semiconductor, hy5du573222afm Datasheet - Page 3

• Manufacturer Part Number: hy5du573222afm
• Description: 256m 8mx32 Gddr Sdram
• Manufacturer: Hynix Semiconductor

DESCRIPTION
The Hynix HY5DU573222AFM is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM which consists
of two 128Mbit(x32) - Multi-chip-, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 8Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
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ORDERING INFORMATION
Rev. 0.5 / Aug. 2003
HY5DU573222AFM-25
HY5DU573222AFM-28
HY5DU573222AFM-33
HY5DU573222AFM-36
HY5DU573222AFM-4
2.5V +/- 5% V
supports 300/275/250MHz
2.8V VDD and VDDQ wide range min/max power
supply supports 400/350Mhz
All inputs and outputs are compatible with SSTL_2
interface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
The signals of Chip select control the each chip with
CS0 and CS1, individually.
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Part No.
DD
and V
Power Supply
DDQ
V
V
V
V
DDQ
DDQ
DD
DD
power supply
2.8V
2.5V
2.8V
2.5V
Frequency
400MHz
350MHz
300MHz
275MHz
250MHz
Clock
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(Both chips do refresh operation, simultaneously)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5 and 4,3 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
interface
SSTL_2
HY5DU573222AFM
12mmx12mm
144Ball FBGA
Package
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