ST7-STICK45 STMICROELECTRONICS [STMicroelectronics], ST7-STICK45 Datasheet
ST7-STICK45
Related parts for ST7-STICK45
ST7-STICK45 Summary of contents
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... Timers ■ – One 8-bit Lite Timer (LT) with prescaler in- cluding: watchdog, 1 realtime base and 1 in- put capture. Device Summary ST7LITESxY0 (ST7SUPERLITE) Features ST7LITES2Y0 Program memory - bytes 1K RAM (stack) - bytes 128 (64) Data EEPROM - bytes ...
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... ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 ...
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... DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 112 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 114 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD- WARE WATCHDOG OPTION 121 16 ...
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To obtain the most recent version of this datasheet, please check at www.st.com Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121. Table of Contents 4/124 1 ...
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... SS RESET ST7SUPERLITE The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes ...
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... ST7LITE0xY0, ST7LITESxY0 2 PIN DESCRIPTION Figure 2. 20-Pin QFN Package Pinout MISO/AIN2/PB2 SCK/AIN1/PB1 Figure 3. 16-Pin SO and DIP Package Pinout k SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 6/124 RESET ei1 ei2 ei0 RESET 3 SS/AIN0/PB0 ei3 ...
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... ST7LITE0xY0, ST7LITESxY0 1) , ana = analog Main Function Alternate Function (after reset) Ground Main power supply Top priority non maskable interrupt (active low) ADC Analog Input 0 or SPI Slave X Port B0 Select (active low) ADC Analog Input 1 or SPI Clock ...
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... ST7LITE0xY0, ST7LITESxY0 Pin n° Pin Name 15 14 PA2/ATPWM0 I PA1 I PA0/LTIC I/O C Note: In the interrupt input column, “ei umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 8/124 1 Level Port / Control ...
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... The available memory locations consist 128 bytes of register locations, 128 bytes of RAM, 128 bytes of data EEPROM and up to 1.5 Kbytes of user program memory. The RAM space in- cludes bytes for the stack from 0C0h to 0FFh. Figure 4. Memory Map (ST7LITE0x) 0000h HW Registers (see Table 007Fh ...
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... ST7LITE0xY0, ST7LITESxY0 REGISTER AND MEMORY MAP (Cont’d) Figure 5. Memory Map (ST7SUPERLITE) 0000h 007Fh 0080h 00FFh 0100h FBFFh FC00h FFDFh FFE0h Interrupt & Reset Vectors FFFFh 10/124 1 0080h HW Registers (see Table 2) 00BFh RAM 00C0h (128 Bytes) 00FFh Reserved FC00h FDFFh Flash Memory ...
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... Flash Control/Status Register Data EEPROM Control/Status Register SPI Data I/O Register SPI Control Register SPI Control/Status Register A/D Control Status Register A/D Data Register A/D Amplifier Control Register External Interrupt Control Register Main Clock Control/Status Register RC oscillator Control Register ST7LITE0xY0, ST7LITESxY0 Reset Remarks Status 1) 00h R/W 00h R/W 40h R/W ...
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... ST7LITE0xY0, ST7LITESxY0 Register Address Block 003Ah SI SICSR 003Bh to 007Fh Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. ...
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... ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory contain- ing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. – Download ICP Driver code in RAM from the ICCDATA pin – Execute ICP Driver code in RAM to program ...
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... Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the CLKIN pin of the ST7 when the clock is not available in the ap- plication or if the selected clock option is not pro- grammed in the option byte. Caution: During normal operation, ICCCLK pin ...
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... Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC proto- col, refer to the ST7 Flash Programming Refer- ence Manual and to the ST7 ICC Protocol Refer- ence Manual 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write ...
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... ST7LITE0xY0, ST7LITESxY0 5 DATA EEPROM 5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 7. EEPROM Block Diagram EECSR 0 0 ADDRESS DECODER ADDRESS BUS 16/124 1 5 ...
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... E2LAT bit not possible to read the latched data. This note is illustrated by the E2LAT = 0 (with the same 11 MSB of the address) START PROGRAMMING CYCLE CLEARED BY HARDWARE ST7LITE0xY0, ST7LITESxY0 Figure WRITE MODE E2LAT = 1 E2PGM = 0 WRITE BYTES IN EEPROM AREA E2LAT=1 ...
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... ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 2 Figure 9. Data E PROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION Byte 1 Byte 2 Writing data latches E2LAT bit Set by USER application E2PGM bit Note programming cycle is interrupted (by RESET action), the integrity of the data in memory will not be guaranteed ...
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... Option Byte, the entire Pro- gram memory and EEPROM is first automatically erased. Note: Both Program Memory and data EEPROM are protected using the same option bit. READ OPERATION NOT POSSIBLE ERASE CYCLE WRITE CYCLE t PROG ST7LITE0xY0, ST7LITESxY0 READ OPERATION POSSIBLE LAT PGM 19/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software cleared by hard- ware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared ...
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... Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 0 ACCUMULATOR 0 X INDEX REGISTER 0 Y INDEX REGISTER PCL 0 PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER ST7LITE0xY0, ST7LITESxY0 X = Undefined Value 21/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions ...
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... A subroutine call occupies two locations and an in- terrupt five locations in the stack area. PUSH PCH PCH PCL PCL PCH PCH PCL PCL ST7LITE0xY0, ST7LITESxY0 Figure 12. POP Y IRET PCH SP PCL PCH PCH SP PCL PCL RET or RSP 23/124 1 ...
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... Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (en- abled by option byte) 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT The ST7 contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage. It must be calibrated to obtain the fre- quency required in the application. This is done by software writing a calibration value in the RCCR (RC Control Register) ...
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... The fastest method is to use a di- 0 chotomy starting with 80h. 0 MCO SMS CR6 CR5 ST7LITE0xY0, ST7LITESxY0 or f /32. OSC OSC f CPU = OSC f /32) CPU = OSC CR6 CR5 CR4 CR3 4 3 ...
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... ST7LITE0xY0, ST7LITESxY0 SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d) Figure 14. Clock Management Block Diagram CR7 CR6 CR5 Tunable 1% RC Oscillator /2 DIVIDER CLKIN f OSC /32 DIVIDER 7 26/124 1 CR4 CR3 CR2 CR1 CR0 PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz Option byte 8-BIT LITE TIMER COUNTER ...
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... These sources act on the RESET pin and it is al- ways kept low during the delay phase. The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 15: Active Phase depending on the RESET source ■ ...
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... ST7LITE0xY0, ST7LITESxY0 RESET SEQUENCE MANAGER (Cont’d) 7.4.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R ON This pull-up has no fixed value but varies in ac- cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details ...
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... INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, ...
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... ST7LITE0xY0, ST7LITESxY0 INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 6. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 Not used 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ei2 External Interrupt 2 4 ei3 External Interrupt 3 ...
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... IS10 IS01 IS00 Table 7. Interrupt Sensitivity Bits ISx1 ISx0 ST7LITE0xY0, ST7LITESxY0 External Interrupt Sensitivity 0 Falling edge & low level 1 Rising edge only 0 Falling edge only 1 Rising and falling edge 31/124 1 ...
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... The Low Voltage Detector function (LVD) gener- ates a static reset when the V below a V reference value. This means that IT-(LVD) it secures the power-up as well as the power-down keeping the ST7 in reset. The V reference value for a voltage drop is IT-(LVD) lower than the V reference value for power- ...
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... Figure 20. Reset and Supply Management Block Diagram RESET SEQUENCE RESET MANAGER (RSM WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT SICSR LOC KED 7 LOW VOLTAGE DETECTOR (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) ST7LITE0xY0, ST7LITESxY0 STATUS FLAG AVD Interrupt Request LVD AVD AVD 33/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply voltage (V ). The V AVD IT-(AVD) for falling voltage is lower than the V ence value for rising voltage in order to avoid par- asitic detection (hysteresis) ...
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... The AVD remains active but the AVD inter- rupt cannot be used to exit from Halt mode. 8.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is ST7LITE0xY0, ST7LITESxY0 set and the interrupt mask in the CC register is re- set (RIM instruction). Enable Event ...
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... ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0x00 (0xh) 7 LOCK Bit 7:4 = Reserved, must be kept cleared. Bit 3 = LOCKED PLL Locked Flag This bit is set by hardware cleared only by a power-on reset set automatically when the PLL reaches its operating frequency ...
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... OSC From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 22. Power Saving Mode Transitions RUN ...
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... ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts ...
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... Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from ACTIVE-HALT mode. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ST7LITE0xY0, ST7LITESxY0 ACTIVE 256 CPU HALT CYCLE DELAY RESET ...
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... ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when active halt mode is disa- bled. The MCU can exit HALT mode on reception of ei- ther a specific interrupt (see Table 6, “Interrupt Mapping,” ...
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... For the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ST7LITE0xY0, ST7LITESxY0 – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure advised to clear all occurrences of the data value 0x8E from memo- ry ...
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... ST7LITE0xY0, ST7LITESxY0 10 I/O PORTS 10.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output ...
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... DR register. Open-drain Notes: Vss – Input pull-up configuration can cause unexpect- Floating ed value at the input of the alternate peripheral input. – When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. ST7LITE0xY0, ST7LITESxY0 43/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Figure 29. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table 9. I/O Port Mode Options Configuration Mode Floating with/without Interrupt Input Pull-up with/without Interrupt ...
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... DR register content. Hardware Configuration V DD PULL- CONDITION INTERRUPT CONDITION ST7LITE0xY0, ST7LITESxY0 DR REGISTER ACCESS W DR REGISTER DATA BUS R ALTERNATE INPUT FROM OTHER PINS EXTERNAL INTERRUPT SOURCE (ei POLARITY SELECTION ANALOG INPUT DR REGISTER ACCESS R/W ...
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... ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog ...
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... Reset Value PBDDR MSB 0004h Reset Value PBOR MSB 0005h Reset Value ST7LITE0xY0, ST7LITESxY0 LSB 0 0 LSB 0 0 LSB ...
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... ST7LITE0xY0, ST7LITESxY0 11 ON-CHIP PERIPHERALS 11.1 LITE TIMER (LT) 11.1.1 Introduction The Lite Timer can be used for general-purpose timing functions based on a free-running 8-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watch- dog function. 11.1.2 Main Features Realtime Clock ■ – 8-bit upcounter – ...
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... Watchdog is disabled (reset state). If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction recommended before executing the HALT instruc- tion to refresh the WDG counter, to avoid an unex- pected WDG reset immediately after waking up the microcontroller. ST7LITE0xY0, ST7LITESxY0 49/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) Figure 32. Watchdog Timing Diagram f WDG WDGD BIT INTERNAL WATCHDOG RESET 50/124 1 HARDWARE CLEARS WDGD BIT t WDG (2ms @ 8 MHz f ) OSC SOFTWARE SETS WDGD BIT WATCHDOG RESET ...
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... Timebase and IC events generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM in- struction). 4µs ) OSC 02h 03h 04h 05h xxh ST7LITE0xY0, ST7LITESxY0 Enable Exit Event Control from Flag Bit Wait TBF TBIE Yes ...
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... ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) 11.1.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Reset Value: 0x00 0000 (x0h) 7 ICIE ICF TB TBIE TBF Bit 7 = ICIE Interrupt Enable This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled ...
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... CK1 CK0 OVF f COUNTER 12-BIT UPCOUNTER CNTR 12-BIT AUTORELOAD VALUE ATR CMPF0 bit OE0 bit 0 COMP- PARE 1 ST7LITE0xY0, ST7LITESxY0 OVF INTERRUPT REQUEST 0 OVFIE CMPIE CMP INTERRUPT REQUEST CMPF0 Update on OVF Event OE0 bit OP0 bit POL- f PWM ARITY ) CPU ...
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... ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.3 Functional Description PWM Mode This mode allows a Pulse Width Modulated sig- nals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output push- pull alternate function ...
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... The interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). 2. only if CK0=1and CK1=0 ST7LITE0xY0, ST7LITESxY0 FFFh FFDh FFEh Description The input frequency is divided ...
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... ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATC- SR) Read / Write Reset Value: 0000 0000 (00h CK1 CK0 Bit 7:5 = Reserved, must be kept cleared. Bit 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset ...
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... This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 regis- ter value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. ST7LITE0xY0, ST7LITESxY0 Figure 35). In Output CONTROL/STATUS ...
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... ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h Table 14. Register Map and Reset Values Address Register Label (Hex.) ATCSR 0D Reset Value CNTRH 0E Reset Value CNTRL CN7 0F Reset Value ...
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... Read Buffer Write MASTER CONTROL SERIAL CLOCK GENERATOR ST7LITE0xY0, ST7LITESxY0 shows the serial peripheral interface put by SPI slaves This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven by stand- ard I/O ports on the master MCU ...
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... ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 38. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first) ...
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... not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Byte 1 Byte 2 SSM bit SSI bit 1 SS internal 0 ST7LITE0xY0, ST7LITESxY0 Figure 39 made free for standard I/O by manag- Section 11.3.5.3). Byte 3 61/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to ...
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... SPE bit. CPHA =1 Bit 4 Bit3 Bit 6 Bit 5 Bit 4 Bit3 Bit 6 Bit 5 CPHA =0 Bit 4 Bit3 Bit 6 Bit 5 Bit 4 Bit3 Bit 6 Bit 5 ST7LITE0xY0, ST7LITESxY0 41, shows an SPI transfer with the four Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit 63/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5 Error Flags 11.3.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an SPI interrupt re- quest is generated if the SPIE bit is set. ...
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... SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. SS SCK SCK Slave Slave MCU MCU MOSI MISO MOSI ST7LITE0xY0, ST7LITESxY0 SS SS SCK Slave MCU MISO MOSI MISO 65/124 1 ...
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... Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode Slave selec- tion is configured as external (see 11.3.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode ...
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... SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 15. SPI Master mode SCK Frequency Table 15 SPI Master Mode Fault ST7LITE0xY0, ST7LITESxY0 edge. edge. Serial Clock SPR2 ...
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... ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register ...
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... MSB 31 Reset Value SPICR SPIE 32 Reset Value SPICSR SPIF 33 Reset Value SPE SPR2 MSTR WCOL OVR MODF ST7LITE0xY0, ST7LITESxY0 CPOL CPHA SPR1 SOD LSB x x SPR0 x x SSM SSI 0 0 69/124 ...
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... Data register (DR) which contains the results ■ Conversion complete status flag ■ On/off bit (to reduce consumption) ■ Fixed gain operational amplifier (x8) (not ■ available on ST7LITES5 devices) 70/124 1 11.4.3 Functional Description 11.4.3.1 Analog Power Supply The block diagram is shown in V and V are the high and low level reference ...
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... EOC SPEED ADON AIN0 AIN1 ANALOG MUX AINx (ADCAMP Register) DIV SLOW bit 0 0 CH2 CH1 3 HOLD CONTROL R ADC AMPSEL bit ADCDR D7 ST7LITE0xY0, ST7LITESxY0 f ADC (ADCAMP Register) 0 ADCCSR CH0 ANALOG TO DIGITAL CONVERTER C ADC 71/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.4.3.3 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ( greater than or equal AIN to V (high-level voltage reference) then the ...
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... SPEED bit to configure the ADC clock speed as shown on the table below. CH2 CH1 CH0 Bit 2 = AMPSEL Amplifier Selection Bit This bit is set and cleared by software. For ST7LITES5 devices, this bit must be kept at its re set value (0 Amplifier is not selected 0 ...
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... ST7LITE0xY0, ST7LITESxY0 Table 17. ADC Register Map and Reset Values Address Register Label (Hex.) ADCCSR EOC 34h Reset Value ADCDR 35h Reset Value ADCAMP 36h Reset Value 74/124 SPEED ADON CH2 ...
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... All memory to memory in- structions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) byte,#5 The ST7 Assembler optimizes the use of long and short addressing modes. Destination/ Syntax Source ...
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... ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For Interrupt (Low Power ...
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... ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register value ( with a pointer value located in memory. The point- er address follows the opcode ...
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... ST7LITE0xY0, ST7LITESxY0 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call ...
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... M) reg A = FFH-A reg, M dec Y reg, M Pop CC inc X reg [TBL.w] jrf * Unsigned < Jmp if unsigned >= Unsigned > ST7LITE0xY0, ST7LITESxY0 Src ...
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... C => Dst => C reg Max allowed <= Dst <= 0 reg <= Dst <= 0 reg => Dst => C reg, M Dst7 => Dst => C reg Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt XOR M A Src ...
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... The loading conditions used for pin parameter measurement are shown in Figure Figure 46. Pin loading conditions C L 13.1.5 Pin input voltage The input voltage measurement on a pin of the de- vice is described in Figure 47. Pin input voltage =25°C A ≤5.5V DD ≤3.6V DD =2.7V (for the DD 46. ST7 PIN ST7LITE0xY0, ST7LITESxY0 Figure 47. ST7 PIN V IN 81/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics Symbol Supply voltage DD SS ...
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... Note: For further information on clock management and f on page 24 Conditions MHz. max., OSC MHz. max. OSC ≤5.5V 3.3V≤ <3.3V 2.4V≤V DD 2.7 3.3 3.5 4.0 CLKIN ST7LITE0xY0, ST7LITESxY0 Min Max 2.4 5.5 3.3 5 Supply Voltage DD FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA) SUPPLY VOLTAGE [V] 5.5 4 ...
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... ST7LITE0xY0, ST7LITESxY0 13.3.2 Operating Conditions with Low Voltage Detector (LVD -40 to 85°C, unless otherwise specified A Symbol Parameter Reset release threshold V IT+ (LVD) (V rise) DD Reset generation threshold V (LVD) IT- (V fall LVD voltage threshold hysteresis hys rise time rate POR DD t Filtered glitch delay on V ...
Page 85
... Internal RC Oscillator and PLL The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter V Internal RC Oscillator operating voltage DD(RC PLL operating voltage DD(x4PLL PLL operating voltage DD(x8PLL) t PLL Startup time STARTUP The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables. ...
Page 86
... 1MHz@T =25° 1MHz@T =40 to +85° 1MHz RC ) =25°C A and V pins as close as possible to the ST7 device max. 10% until t has elapsed. See PLL STAB = -40 to +85° Min =25° 3. -25 -15 700 0.7 =2 ...
Page 87
... V (Calibrated with RCCR0 25°C 3.4 3.6 3.8 4 Figure 52. RC Osc Freq 1.80 1.60 1.40 1.20 -45° 0° 1.00 25° 0.80 90° 0.60 105° 0.40 130° 0.20 0. w(JIT) ST7LITE0xY0, ST7LITESxY0 Typical RC oscillator Accuracy Temperature (° tested in production * and RCCR Value DD 2.4 2 ...
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... ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Figure 54. PLLx4 Output vs CLKIN frequency 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 2 External Input Clock Frequency (MHz) Note /2*PLL4 OSC CLKIN 88/124 1 Figure 55. PLLx8 Output vs CLKIN frequency 11.00 9.00 7.00 3.3 3 5.00 2.7 3.00 1.00 2.5 3 Note: f OSC 0.85 0.9 1 1.5 2 External Input Clock Frequency (MHz /2*PLL8 CLKIN 5.5 5 4.5 4 2.5 ...
Page 89
... SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- 13.4.1 Supply Current T = -40 to +85°C unless otherwise specified A Symbol Parameter ...
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... ST7LITE0xY0, ST7LITESxY0 SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 58. Typical I in WAIT vs 8MHz 2.0 4MHz 1.5 1MHz 1.0 0.5 0.0 2.4 2.7 3.7 Vdd (V) Figure 59. Typical I in SLOW-WAIT vs 250kHz 0.70 125kHz 0.60 0.50 62.5kHz 0.40 0.30 0.20 0.10 0.00 2.4 2.7 3.7 Vdd (V) 13.4.2 On-chip peripherals Symbol I 12-bit Auto-Reload Timer supply current DD(AT) I SPI supply current DD(SPI) I ADC supply current when converting DD(ADC) 1 ...
Page 91
... CPU 3) f =8MHz CPU Conditions 4) see Figure 61 4) ≤V ≤ 90% 10 fCLKIN) w(CLKINH) CLKIN ST7LITE0xY0, ST7LITESxY0 . A 2) Min Typ 2 3 250 375 10 1.25 Min Typ 0.7xV DD V 0.3xV the number of t cycles needed to fin- c(INST) CPU t w(CLKINL) ...
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... ST7LITE0xY0, ST7LITESxY0 13.6 MEMORY CHARACTERISTICS T = -40°C to 105°C, unless otherwise specified A 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Program Memory Symbol Parameter V Operating voltage for Flash write/erase DD Programming time for 1~32 bytes t prog Programming time for 1.5 kBytes 4) t Data retention ...
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... DD emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Conditions =5V, T =+25° SO16 package, conforming to SAE J 1752/3 ST7LITE0xY0, ST7LITESxY0 Conditions =5V, T =+25°C, f =8MHz OSC conforms to IEC 1000-4-2 =5V, T =+25°C, f =8MHz ...
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... ST7LITE0xY0, ST7LITESxY0 EMC CHARACTERISTICS (Cont’d) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. ESD absolute maximum ratings Symbol Ratings Electro-static discharge voltage V ESD(HBM) ...
Page 95
... Between 10% and 90% 4) Figure 66). Static peak current value taken at a fixed V ST7XXX UNUSED I/O PORT noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. with 4.5 5 5.5 6 ST7LITE0xY0, ST7LITESxY0 unless otherwise specified. A Min Typ V 0.3xV - 0.3 SS 0.7xV V DD 400 400 50 120 160 ...
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... ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 65 Output low level voltage for a high sink I/O pin ...
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... Figure 66. Typical V DD -45°C 0°C 25°C 90°C 130°C 3 Figure 67. Typical V =5V (standard) DD -45°C 0°C 25°C 90°C 130° Figure 68. Typical V ST7LITE0xY0, ST7LITESxY0 at V =5V (high-sink 2.50 2.00 1.50 1.00 0.50 0. lio (mA =3V (high-sink 1.20 1.00 0.80 0.60 0.40 0.20 0. ...
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... ST7LITE0xY0, ST7LITESxY0 Figure 69. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio(mA) Figure 70. Typical 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio (mA) Figure 73. Typical V vs 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 2.4 2.7 VDD (V) 98/124 =2.7V Figure 71. Typical V DD -45°C 0°C 25°C 90°C 130°C -2 Figure 72. Typical =3V DD -45°C 0°C 25°C 90°C 130° (standard I/Os) ...
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... VDD (V) Figure 75. Typical 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 4 VDD (high-sink I/Os) DD 1.00 0.90 0.80 -45 0.70 0.60 0°C 0.50 25°C 0.40 90°C 0.30 130°C 0.20 0.10 0. 1.10 1.00 0.90 -45°C 0.80 0°C 25°C 0.70 90°C 130°C 0.60 0.50 0.40 5 ST7LITE0xY0, ST7LITESxY0 2 VDD (V) 2.4 2 VDD (V) -45 0°C 25°C 90°C 130°C -45°C 0°C 25°C 90°C 130°C 99/124 1 ...
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... ST7LITE0xY0, ST7LITESxY0 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40°C to 105°C, unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low level voltage OL R Pull-up equivalent resistor ON t Generated reset pulse duration ...
Page 101
... Note 1: – The reset network protects the device against parasitic resets. – The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). – Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V max ...
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... ST7LITE0xY0, ST7LITESxY0 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK = SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise and fall time t f(SCK setup time su(SS hold time ...
Page 103
... MSB OUT BIT6 OUT t su(SI) h(SI) MSB c(SCK) t w(SCKH) t w(SCKL) t h(MI) MSB IN BIT6 IN t v(MO) MSB OUT BIT6 OUT and 0.7xV DD ST7LITE0xY0, ST7LITESxY0 t h(SS) t h(SO) t r(SCK) t f(SCK) LSB OUT LSB IN BIT1 IN t r(SCK) t f(SCK) LSB IN t h(MO) LSB OUT . DD t dis(SO) see note 2 See note 2 ...
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... ST7LITE0xY0, ST7LITESxY0 13.11 8-BIT ADC CHARACTERISTICS T = -40°C to 85°C, unless otherwise specified A Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ADC enable STAB t Conversion time (t CONV ...
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... Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted. ST7LITE0xY0, ST7LITESxY0 AIN Cain 10 nF Cain 22 nF Cain ...
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... ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V =5. -40°C to 85°C, unless otherwise specified A Symbol Parameter E Total unadjusted error Offset error Gain Error G E Differential linearity error D E Integral linearity error L E Total unadjusted error T 2) ...
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... IDEAL 6 7 100 101 102 103 250 mV ST7LITE0xY0, ST7LITESxY0 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line E =Total Unadjusted Error: maximum deviation T between the actual and the ideal transfer curves. E =Offset Error: deviation between the first actual O transition and the first ideal one ...
Page 108
... ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Vout (ADC input) Vmax Vmin 0V 0V Symbol Parameter V Amplifier operating voltage DD(AMP) V Amplifier input voltage IN V Amplifier offset voltage OFFSET V Step size for monotonicity STEP Output Voltage Response Linearity Gain factor Amplified Analog input Gain ...
Page 109
... JEDEC Standard 14.1 PACKAGE MECHANICAL DATA Figure 86. 20-Lead Very thin Fine pitch Quad Flat No-Lead Package ST7LITE0xY0, ST7LITESxY0 JESD97. The maximum ratings related to solder- ing conditions are also marked on the inner box la- bel. ...
Page 110
... ST7LITE0xY0, ST7LITESxY0 Figure 87. 16-Pin Plastic Dual In-Line Package, 300-mil Width Figure 88. 16-Pin Plastic Small Outline Package, 150-mil Width 110/124 45× α Dim Min Typ Max A 5. 0.38 A2 2.92 3.30 4.95 0.1150 0.1299 0.1949 b 0 ...
Page 111
... The power dissipation of an application can be defined by the user with the formula: P where P is the chip internal power (I INT ports used in the application. Ratings SO16 DIP16 and P is the port power dissipation depending on the DD DD PORT ST7LITE0xY0, ST7LITESxY0 Value 95 TBD 150 500 = ( thJA =P D INT Unit ° ...
Page 112
... Note 1: Configuration available for ST7LITE0x de- vices only. 112/124 The FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the cus- tomer using the Option Bytes while the FASTROM devices are factory-configured. ...
Page 113
... Bit 4 = OSC RC Oscillator selection 0: RC oscillator oscillator off Note: If the RC oscillator is selected, then to im- prove clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100nF, between the V close as possible to the ST7 device. PLL Typ f off 0.7MHz @3V x4 2.8MHz @3V ...
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... ST7LITE0xY0, ST7LITESxY0 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the FASTROM con- tents and the list of the selected options (if any). The FASTROM contents are to be sent on dis- kette electronic means, with the S19 hexa- decimal file generated by the development tool. All unused bytes must be set to FFh ...
Page 115
... Figure 89. Ordering information scheme Example: Family ST7 Microcontroller Family Memory type F: Flash P: FASTROM Sub-family LITES2, LITES5, LITE02, LITE05 or LITE09 No. of pins Memory size (LITESx versions) or 1.5K (LITE0x versions) Package B = DIP QFN Temperature range 6 = -40 ° °C Shipping Option TR = Tape & ...
Page 116
... ST7LITE0xY0, ST7LITESxY0 ST7LITE0xY0 AND ST7LITESxY0 FASTROM MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 117
... ST7 Toolset from STMicroelec- tronics, which includes the STVD7 integrated de- velopment environment (IDE) with high-level lan- 15.3.5 Order codes for ST7LITE0/ST7LITES development tools Table 23. Development tool order codes for the ST7LITE0/ST7LITES family MCU In-circuit Debugger, RLink Series Starter Kit ST7FLITE02, ...
Page 118
... EMULATED 16-BIT SLAVE SPI AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS ...
Page 119
... EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA- AN1530 TOR AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE ...
Page 120
... ST7 CUSTOMER ROM CODE RELEASE INFORMATION AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY ...
Page 121
... In ST tools, this mode is called "ICP OPTIONS DISABLED". Sockets on ST programming tools (such as ST7MDT10-EPB) are controlled using "ICP OP- TIONS DISABLED" mode. Devices can therefore be reprogrammed by plugging them in the ST Pro- gramming Board socket, whatever the watchdog configuration ...
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... ST7LITE0xY0, ST7LITESxY0 17 REVISION HISTORY Table 25. Revision History Date Revision Revision number incremented from 2.5 to 3.0 due to Internal Document Management Sys- tem change Changed all references of ADCDAT to ADCDR Added EMU3 Emulator Programming Capability in Clarification of read-out protection Altered note 1 for Alteration page 90 Removed sentence relating to an effective change only after overflow for CK[1:0], ...
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... ST7LITE0xY0, ST7LITESxY0 section 10.2.1 on page 42 Figure 61 on page 91 section 11.2.6 on page 56 82, note “negative injection not allowed on Figure 2 on page 6 and ...
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... ST7LITE0xY0, ST7LITESxY0 Notes: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...