cxa3250an Sony Electronics, cxa3250an Datasheet - Page 23

• Manufacturer Part Number: cxa3250an
• Description: All Band Tv Tuner Ic With On-chip Pll
• Manufacturer: Sony Electronics

4.) 3-Wire Bus Control
19-bit data format
4-1) 18-bit data transfer
4-2) 19-bit data transfer
ENABLE
CLOCK
18-bit data format
ENABLE
The following transfer bit length formats are automatically identified during 3-wire bus control.
DATA
Invalid data
CLOCK
18 bits : Band data (4 bits) + frequency data (14 bits)
19 bits : Band data (4 bits) + frequency data (15 bits)
27 bits : Band data (4 bits) + frequency data (15 bits) + test data (8 bits)
Data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the
falling edge of the enable signal.
The clocks during the enable period are counted, and when 18 bits have been loaded, the
programmable divider “M9” data is set to “0” and the reference divider frequency division ratio is
automatically set to “1/80” when the BYP/MS pin voltage is V
open.
DATA
Data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the
falling edge of the enable signal.
The clocks during the enable period are counted, and when 19 bits have been loaded, the reference
divider frequency division ratio is automatically set to “1/80” when the BYP/MS pin voltage is V
“1/128” when the BYP/MS pin is DC open.
Invalid data
BS4 BS3 BS2 BS1
Band switch data
1
BS4 BS3 BS2 BS1 M8
Band switch data
1
Time
Time
4
4
M9
5
5
M8
M7
M7
M6
M6
M5
M5
—23—
M4
M4
M3
Frequency data
Frequency data
M3
M2
M2
M1
CC
M1
or to “1/64” when the BYP/MS pin is DC
M0
M0
S4
S4
S3
S3
S2
S2
S1
S1
S0
18
S0
19
Invalid data
Latch
Invalid data
CXA3250AN
Latch
CC
or to