cxd3220r Sony Electronics, cxd3220r Datasheet - Page 27

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

(5) Last quadlet of the transmitted packet Write
Let the last quadlet of the Quadlet Write request packet be "12345678h".
This is written in the CFR ATFWrite (confirm write) register.
The Quadlet Write request packet is stored in the ATF as shown above. When the bus is enabled, the
CXD3220R transmits automatically. If transmit does not take place, the CFR interrupt register (0Ch to 0Fh)
must be read to confirm if the ATStk bit or TCErr bit is high. If these bits are high, the packet stored in the ATF
may not be correct.
For either of ATStk or TCErr above, the next packet for write will not be transmitted even if it is correct.
At this time "1" must be written in the CFR Async Status register ClearATF bit in order to clear the ATF.
Transmit is then enabled when a correct packet is written.
ATStk = High: If the first quadlet of the packet was not written in the CFR ATFWrite (first quadlet of the
TCErr = High: A value that is not a Transaction code able to be transmitted by Asynchronous packet is
ADDRESS
DATA
XWR
XCS
packet) register but was written in the ATFWrite/ARFRead register or the ATFWrite (confirm
write) register.
written in the tCode field of the first quadlet of the packet.
The Transaction codes that can be transmitted as Asynchronous packets are any of (0, 1, 2,
4, 5, 6, 7, 9, B, Eh).
7Ch
12h
– 27 –
7Dh
34h
7Eh
56h
78h
7Fh
CXD3220R