cxd3220r Sony Electronics, cxd3220r Datasheet - Page 29

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

In the above example, ArfEmpty is low.
Data read is possible because the ArfEmpty bit is low.
(3) First quadlet of the received packet Read
The CFR ATFWrite/ARFRead register is read.
The data read is "FFC00000h".
At this time, the ArfDc bit is high (from (2) above), so this quadlet is the first quadlet.
(2) Confirming that the received packet was stored correctly in FIFO
The CFR Async Status register (1C to 1Fh) is read to confirm that the 26th bit (ArfEmpty bit) is low.
If this bit is high it means that reception may be in progress (all quadlets have not arrived). In this state, do not
read the ARF read register (74 to 77h). Wait some time and again read the Async Status register to confirm
the ArfEmpty bit.
ADDRESS
ADDRESS
DATA
DATA
XCS
XRD
XCS
XRD
This indicates no ArfEmpty flags up.
xxxxx0xxb
FFh
1Ch
74h
75h
C0h
1Dh
– 29 –
76h
00h
1Eh
77h
00h
1Fh
CXD3220R