ST72325 STMICROELECTRONICS [STMicroelectronics], ST72325 Datasheet - Page 7

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ST72325

Manufacturer Part Number
ST72325
Description
8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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1 INTRODUCTION
The ST72F325 Flash and ST72325 ROM devices
are members of the ST7 microcontroller family de-
signed for mid-range applications.
They are derivatives of the ST72321 and ST72324
devices, with enhanced characteristics and robust
Clock Security System.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
Figure 1. Device Block Diagram
(8 bits on AR devices)
(2 bits on C/J/K devices)
1)
(8 bits on AR devices)
(6 bits on C/J devices)
(5 bits on K devices)
(6 bits on C/J devices)
(2 bits on K devices)
(8 bits on AR devices)
ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.
RESET
PF7:0
OSC1
OSC2
V
V
PD7:0
EVD
PE7:0
AREF
V
V
V
TLI
SSA
DD
SS
PP
MCC/RTC/BEEP
8-BIT CORE
10-BIT ADC
CONTROL
TIMER A
PORT D
PORT F
PORT E
BEEP
AVD
OSC
ALU
LVD
SCI
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Main Differences with ST72321:
– TQFP48 and TQFP32 packages
– Clock Security System
– Internal RC, Readout protection, LVD and PLL
– Negative current injection not allowed on I/O port
– External interrupts have Exit from Active Halt
without limitations
PB0 (instead of PC6).
mode capability.
(512 - 2048 Bytes
(16K - 60K Bytes
DEBUG MODULE
WATCHDOG
PROGRAM
PWM ART
MEMORY
TIMER B
PORT C
PORT A
PORT B
RAM
I2C
SPI
1)
1)
)
)
(8 bits)
PC7:0
(8 bits on AR devices)
(5 bits on C/J devices)
(4 bits on K devices)
(8 bits on AR devices)
PA7:0
PB7:0
(5 bits on C/J devices)
(3 bits on K devices)
ST72325
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