ST16 STMICROELECTRONICS [STMicroelectronics], ST16 Datasheet
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... ST16-19RFRDCS CHIP SET INTERFACE SPECIFICATION FSD_CHIPSET_B/0104VP2 ...
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The present document contains CONFIDENTIAL INFORMATION. USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. ST PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF STMicroelectronics. ...
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FSD_CHIPSET_B/0104VP2 DIFFERENCES BETWEEN: FSD_CHIPSET_B/0006VP1 AND FSD_CHIPSET_B/0104VP2 DESCRIPTION OF THE MODIFICATION Definition modification of the signal Tx-start Modification of the figure 4 Note: other modifications which are only editorial are not described in this table. CHIP SET INTERFACE SPECIFICATION PARAGRAPH ON ...
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CHIP SET INTERFACE SPECIFICATION TABLE OF CONTENTS 1 FPGA & MCU INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FSD_CHIPSET_B/0104VP2 LIST OF TABLES Table 1 : Interface timing ............................................................................................................. 4 Table 2 : Control register description ........................................................................................... 7 Table 3 : Reception status register description ............................................................................ 8 Table 4 : FPGA pin out ................................................................................................................ 8 CHIP SET INTERFACE SPECIFICATION ...
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CHIP SET INTERFACE SPECIFICATION LIST OF FIGURES Figure 1 FPGA write access chronogram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... FPGA (start up of the reader) or when any parameter has to be modified. For later transmissions, the control registers don’t need initialised. The control Register Description is available in table 2. FSD_CHIPSET_B/0104VP2 This is a Preliminary Data on a new product now in development or undergoing evaluation. Details are subject to change with- out noctice. CHIP SET INTERFACE SPECIFICATION ST16-19RFRDCS PRELIMINARY DATA 1/15 ...
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... ST16-19RFRDCS 1.2.2 Interface signals definition The signals used for the interface between FPGA & MCU, in transmission and reception, are: Mic_Data(7:0): Data bidirectional bus. Mic_strb_b: FPGA strobe signal (Activ low) used to sample the data. This signal is sent by the MCU to the FPGA Mic_RW: Writing/Reading signal (’1’=reading, ’0’=writing). ...
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... Acquisition of the first byte In the figure 2, prior to sending data the FPGA takes the Rx_IRQ_EOF line low to indicate to the MCU that the data can be recuperated Control register writing Data writing Acquisition of the next bytes, except the last one ST16-19RFRDCS 3/15 ...
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... ST16-19RFRDCS Figure 3 FPGA read access chronogram for last byte Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_start Tx_fifo_empty Before sending the last byte the FPGA takes the Rx_fifo_empty line high to indicate to the MCU that this is the last data. 1.3.5 MCU interface timings The following board provides interface timings (cf previous chronogram) ...
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... Cfg_Irq_High: Interrupt Pulse Polarity (’0’=Low, ’1’=High). In order to be able to test the Card Reader functionality at power-on, it’s possible to connect the transmis- sion on the reception inside the FPGA (Loop Mode). Cfg_Loopback: Connection of the transmission on the reception. (’1’= Connection, ’0’= Normal Running) ST16-19RFRDCS 5/15 ...
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... ST16-19RFRDCS 1.5 STATUS REGISTER There is only one status register (for reception). This register can be read at the end of each reception. Its contents is modified by the end of frame interruption. It provides the status of the last received frame. In order to access this register, after the last byte received in reception, take the Mic_Ctrl_Data line high and then read the data. Rx_Speed_Value: Reception Rate (" ...
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... Number of d’EGT bits '0' = CRC automatic '0' = SOF of 10 bits at ‘0’ '0' = SOF of 2 bits at '1' '0' = EOF of 10 bits at '0' LSB 01000011 ST16-19RFRDCS ’1’ = Pulse Mode ‘1' = Pulse Activ High ‘1' = Loop back ’1’ = External Valid ’1’ = Automatic "01" = 212K " ...
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... ST16-19RFRDCS 1.6.2 Status register The mapping of the different state bits is given by the following table: Table 3 : Reception status register description "Address Reception Control bit [1:0]: Rx_Speed_Value bit 2: Rx_CRC_OK bit 3: Rx_EGT_TooLong ’0 bit 4: Rx_Bad_StopBit bit 5: ST Reserved => read at '0' bit 6: ST Reserved => read at '0' bit 7: ST Reserved => ...
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... FSD_CHIPSET_B/0104VP2 Figure 4 The chip set diagram: Example: If you want to send the data ’19 ’, on the Tx_streamout line you will see this signal: Tx_Streamout 1st Byte CRC : Start_of_Frame Data : 19 Start_Bit Stop_Bit ST16-19RFRDCS 2nd Byte CRC End_of_Frame 9/15 ...
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... ST16-19RFRDCS Example: Inputs and ouputs of the FPGA Figure 5 FPGA reading access chronogram Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_start Tx_fifo_empty t0 t1 Acquisition of the first byte Example: you will find hereafter an example of the Analog front End Output. This is a BPSK signal: Demodout ...
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... The AFE is a Dil 32 with only 12 pins package. In this version, only eight pins are used, the not connected pin will be used for the extension type A (Figure 6). The device requires an external inductor, an external capacitance and resistance in order to resonate at 13.56 MHz. FC= ST16-19RFRDCS 11/15 ...
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... ST16-19RFRDCS Figure 7 shows a typical configuration of the external circuit for the AFE. Figure 6 Pin Configuration: Figure 7 Configuration of external resonant circuit: 2.2 FEATURES The AFE is full ISO 14443 type B compliant: – Frequency of the RF operating field is: Fo= 13,56 MHz +/- 7 kHz – Data rate from card to reader and reader to card: 106 k bits – ...
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... Demodulator Sensibility 2.4 ABSOLUTE MAXIMUM RATINGS Symbol Vcc Maximum operating voltage Tstg Storage temperature range Operating ambient tempera- Ta Parameter Power supply voltage Current consumption Oscillator frequency Frequency stability parameter ture range ST16-19RFRDCS Limits Units 12 140 13.56 MHz +/-100 Ppm 10 rating units ...
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... ST16-19RFRDCS Figure 8 Preliminary Packaging Datasheet: 14/15 FSD_CHIPSET_B/0104VP2 ...
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... STMicroelectronics. © 2001 STMicroelectronics - Printed in France - All Rights Reserved Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. BULL CP8 Patents STMicroelectronics GROUP OF COMPANIES ST16-19RFRDCS 15/15 ...