sp5655 Mitel, sp5655 Datasheet - Page 4

• Manufacturer Part Number: sp5655
• Description: 2?7ghz Bidirectional I2c Bus Controlled Synthesiser
• Manufacturer: Mitel

SP5655
FUNCTIONAL DESCRIPTION
Clock are fed in on the SDA and SCL lines respectively, as
defined by the I
accept new data (write mode) or send data (read mode). The
LSB of the address byte (R/W) sets the device into write mode
if it is low and read mode if it is high. The Tables in Fig. 3
illustrate the format of the data. The device can be pro-
grammed to respond to several addresses, which enables the
use of more than one synthesiser in an I
Table 4 shows how the address is selected by applying a
voltage to P3.
the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are
programmed. When the device is programmed into the read
mode, the controller accepting the data must pull the SDA line
low during all status byte acknowledge periods to read an-
other status byte. If the controller fails to pull the SDA line low
during this period, the device generates an internal STOP
condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
synthesised frequency, while bytes 4 and 5 control the output
port states, charge pump, reference divider ratio and various
test modes.
the first bit of the next byte determines whether that byte is
interpreted as byte 2 or 4; a logic 0 for frequency information
and a logic 1 for control and output port information. When
byte 2 is received the device always expects byte 3 next.
Similarly, when byte 4 is received the device expects byte 5
next. Additional data bytes can be entered without the need
to readdress the device until an I
nised. This allows a smooth frequency sweep for fine tuning
or AFC purposes.
ple, by another device on the bus) then the previously pro-
grammed byte is maintained.
and used to control the division ratio of the 15-bit programmable
divider. This is preceded by a divide-by-16 prescaler and amplifier to
give excellent sensitivity at the local oscillator input, see Fig. 5. The
input impedance is shown in Fig. 7.
ing the programmed division ratio by 16 times the comparison
frequency F
comparator, via a charge pump and varicap drive amplifier,
adjusts the local oscillator control voltage until the output of
the programmable divider is frequency and phased locked to
the comparison frequency.
source capacitively coupled into pin 2, or provided by an on-
chip crystal controlled oscillator. The comparison frequency
F
ence divider. The reference divider division ratio is switchable
4
COMP
The SP5655 is programmed from an I
When the device receives a correct address byte, it pulls
When the device is in write mode bytes 2 and 3 select the
Once the correct address is received and acknowledged,
If the transmission of data is stopped mid-byte (for exam-
Frequency data from bytes 2 and 3 are stored in a 15-bit register
The programmed frequency can be calculated by multiply-
The reference frequency may be generated by an external
is derived from the reference frequency via the refer-
COMP
. When frequency data is entered, the phase
2
C Bus format. The synthesiser can either
2
C stop condition is recog-
2
C Bus. Data and
2
C Bus system.
from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a
logic 1 to 512, a logic 0 for 1024. The SP5655 differs from the
SP5055 in this respect, only 512 being available on the
SP5055. Note that the comparison frequency is 7·8125kHz
when a 4MHz reference is used, and divide by 512 is selected.
current in the charge pump circuit, a logic 1 for 170 A and a
logic 0 for 50 A, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. When the device is frequency
locked, the charge pump current is internally set to 50 A
regardless of CP.
to a logic 1.
amplifier’s output off when it is set to a logic 1.
high. These modes are selected by bits 5, 6 and 7 of byte 4
(TS2, and TS1, TS0) as detailed in Table 5. When T1 is set
low, TS2 and TS1 are assigned a ‘don’t care’ condition, and
TS0 selects the reference divider ratio as previously de-
scribed.
0 for a high impedance output and a logic 1 for low impedance
(on).
READ Mode
the device on the SDA line takes the form shown in Table 2.
logic 1 if the V
(at 25˚C), for example, when the device is initially turned on.
The POR is reset to 0 when the read sequence is terminated
by a stop command. When POR is set high (at low V
programmed information is lost and the output ports are all set
to high impedance.
logic 1 is present if the device is locked, and a logic 0 if the
device is unlocked.
P7, P5 and P4 respectively. A logic 0 indicates a low level and
a logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic 1).
These inputs will then respond to data complying with TTL
type voltage levels.
the 5-level ADC. The ADC can be used to feed AFC informa-
tion to the microprocessor from the IF section of the receiver,
as illustrated in the typical application circuit.
APPLICATION
interface circuits are shown in Fig. 6. The SP5655 is function and
pin equivalent to the SP5055 device apart from the switchable
reference divider, and has much lower power dissipation, im-
proved RF sensitivity and better ESD performance.
Bit 4 of byte 4 (T0) disables the charge pump when it is set
Bit 8 of byte 4 (OS) switches the charge pump drive
Bit 3 of byte 4 (T1) enables various test modes when set
Byte 5 programs the output ports P0 and P3 to P7; a logic
When the device is in read mode the status byte read from
Bit 2 (FL) indicates whether the device is phase locked, a
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
A typical application is shown in Fig. 4. All input/output
Bit 1 (POR) is the power-on reset indicator and is set to a
Bit 2 of byte 4 of the programming data (CP) controls the
CC
supply to the device has dropped below 3V
CC
), the