SI2200-X-GM SILABS [Silicon Laboratories], SI2200-X-GM Datasheet - Page 6

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SI2200-X-GM

Manufacturer Part Number
SI2200-X-GM
Description
RF SYNTHESIZER WITH INTEGRATED VCOS INTEGRATED VCOS
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
Si2200
Table 4. Serial Interface Timing
(V
6
Parameter
SCLK Cycle Time
SCLK Rise Time
SCLK Fall Time
SCLK High Time
SCLK Low Time
SDATA Setup Time to SCLK↑
SDATA Hold Time from SCLK↑
SEN↓ to SCLK↑ Delay Time
SCLK↑ to SEN↑ Delay Time
SEN↑ to SCLK↑ Delay Time
SEN Pulse Width
Notes:
DD
1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.
2. Timing is not referenced to the 50% level of the waveform. See Figure 2.
= 2.7 to 3.6 V, T
SCLK
1
A
= –40 to 85 °C)
80%
50%
20%
2
2
2
2
2
Figure 1. SCLK Timing Diagram
Symbol
t
t
t
t
t
t
hold
en1
en2
en3
t
t
clk
t
t
t
su
w
h
r
f
l
t
r
Rev. 1.0
Test Condition
t
h
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
t
clk
t
f
t
l
Min
40
10
10
10
12
12
10
5
0
Typ
Max
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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