SI3201-X-FS SILABS [Silicon Laboratories], SI3201-X-FS Datasheet - Page 26

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SI3201-X-FS

Manufacturer Part Number
SI3201-X-FS
Description
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
Si3233
2.3.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
converter during a ringing burst is set using the VBATH
register (direct Register 74). VBATH can be set between
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, VBATH must be set larger than the
ringing amplitude. At the end of each ringing burst the
dc-dc converter switches back to active state regulation
as described above.
2.4. Tone Generation
Two digital tone generators are provided in the ProSLIC.
They allow the generation of a wide variety of single or
dual tone frequency and amplitude combinations and
26
Counter
Modulo
OATn
OITn
8 kHz
Clock
16-Bit
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
OITnE
OATnE
Expire
Expire
OAT
OIT
OnE
Figure 11. Simplified Tone Generator Diagram
Cross
Logic
Zero
Logic
Logic
INT
INT
OZn
Zero Cross
OSSn
Logic
Load
OnAE
OnAP
OnIE
OnIP
Preliminary Rev. 0.5
REL*
Register
Enable
Load
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip.
2.4.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 11. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control and status register bits are placed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 25.
16 kHz
Clock
Resonance
Two-Pole
Oscillator
OSCnX
OSCnY
OSCn
Routing
Signal
OnSO
to RX Path

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