SI3201-X-FS SILABS [Silicon Laboratories], SI3201-X-FS Datasheet - Page 83

• Manufacturer Part Number: SI3201-X-FS
• Manufacturer: SILABS [Silicon Laboratories]

Register 107. DC Peak Current Monitor Calibration Result
Reset settings = 0000_1000
Register 108. Enhancement Enable
Reset settings = 0000_0000
Name
Name
Type
Type
Bit
7:4
3:0
Bit
4:3
Bit
Bit
7
6
5
CMDCPK[3:0]
ILIMEN
Reserved
Reserved
ILIMEN
FSKEN
R/W
Name
Name
DCSU
D7
D7
FSKEN
R/W
D6
D6
Read returns zero.
DC Peak Current Monitor Calibration Result.
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 µs. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 16 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 16 kHz.
DC-DC Converter Control Speedup.
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
Read returns zero.
DCSU
R/W
D5
D5
Preliminary Rev. 0.5
D4
D4
D3
D3
Function
Function
LCVE
R/W
D2
D2
CMDCPK[3:0]
R/W
DCFIL
R/W
D1
D1
HYSTEN
R/W
D0
D0
Si3233
83