zl10354 Zarlink Semiconductor, zl10354 Datasheet
zl10354
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zl10354 Summary of contents
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... PC-TV receivers • Portable applications Description The ZL10354 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds, with margin, the performance requirements of all known DVB-T digital terrestrial television standards, including Unified Nordig and DTG. Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc ...
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... OFDM signal reception. All sampling and other internal clocks are derived from a single 20.48 MHz crystal MHz clock input, the tolerance of which may be relaxed as much as 200 ppm. The pinout of the ZL10354 is highly adaptable to allow multiple devices to be connected as a diversity receiver. Any number of ZL10354s can be connected together using the high-speed five-bit diversity data bus in a chain of devices ...
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... Transmission Parameter Signalling (TPS 2.13 Diversity Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.14 De-Mapper 2.15 Symbol and Bit De-Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.16 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.17 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.18 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.19 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.20 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.21 MPEG Transport Interface 3.0 Diversity Operation of ZL10354 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Pin Allocation 4.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 2-Wire Bus 4.1.1 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.2 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.3 Examples of 2-Wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.4 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 Diversity Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 ...
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... Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ZL10354 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 4 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5 - Outline Diversity System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6 - Outline of Dual Diversity/Play-and-Record System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - Basic Interconnections and Serial Address Options for Four ZL10354s on the Same Bus Figure 8 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9 - Timing Diagram for the Diversity Bus with DvrClkInv = Figure 10 - DVB Transport Packet Header Byte ...
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... Table 3 - Pin Names Mode A - diversity first or last device in chain Table 4 - Pin Names Mode B - diversity mid-chain device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5 - Pin Names Mode C - non-diversity use Table 6 - Diversity Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7 - Timing of 2-Wire Bus Table 8 - Diversity Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ZL10354 List of Tables 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Pin & Package Details 1.1 Pin Outline Figure 2 below shows the basic, non-diversity, pin functions of the ZL10354. The device can effectively be set up in seven different pin configurations, so for brevity only this version is shown. ZL10354 Figure 2 - Pin Outline 7 Zarlink Semiconductor Inc. Data Sheet ...
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... AGC2/GPP2/DvVal 41 IRQ/Dv4/Dv0 AGnd 29 MDO0/Dv0/ Dv1 AGnd 32 MDO1/Dv1/ Dv3 AVdd 28 MDO2/Dv2 BKERR 62 MDO3/Dv3/ Dv1 CLK1 4 MDO4/Dv4/ Dv0 CLK2/GPP0 35 MDO5 CVdd 7 MDO6 CVdd 19 MDO7 ZL10354 Function Pin SADD1 33 Vdd SADD0 34 RFLEV CVdd 35 CLK2/GPP0 Vss 36 DATA2/GPP1 PLLVdd 37 CVdd PLLGND 38 Vss XTI 39 CVdd XTO 40 Vss ...
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... BKERR 63 MICLK 11 STATUS (or Dv3/1) 6 IRQ (or Dv4/0) Control pins 4 CLK1 5 DATA1 23 XTI 24 XTO 10 SLEEP N/C 12, 15, 16 Dv2,1,0/2,3,4 17, 18 SADD(1:0) 44 SMTEST ZL10354 63 SMTEST 44 61 STATUS/Dv3/ 11 Dv1 47 Vdd 2 48 Vdd 13 27 Vdd 33 22 Vdd 45 Pin Description I/O MPEG packet start O MPEG/diversity data valid O MPEG/diversity data bus ...
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... PLLVdd 22 PLLGnd 7, 19, 37, 39, 59, 64 CVdd 2, 13, 45, 54, Vdd 14, 20, 25, Vss 38, 40, 46, 55 AVdd 29, 32 AGnd 33 Vdd ZL10354 Pin Description I/O Serial clock tuner I/O Serial data tuner I/O Primary AGC O Secondary AGC I/O General purpose I/O I/O Device reset I Crystal oscillator mode I PLL analog test ...
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... Functional Description A functional block diagram of the ZL10354 OFDM demodulator is shown in Figure 3. This accepts an IF analog signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and frequency synchronization operations are all digital and there are no analog control loops except the AGC. The frequency capture range is large enough for all practical applications ...
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... The algorithms and architectures used in the ZL10354 have been optimized to minimize power consumption. 2.1 Analog-to-Digital Converter The ZL10354 has a high performance 10-bit analog-to-digital converter (ADC) which can sample MHz bandwidth OFDM signal, with its spectrum centred at: • 36.17 MHz IF • ...
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... The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being established. This is one of the features of ZL10354 used to minimize acquisition time. A robust AGC lock mechanism is provided and the other parts of the ZL10354 begin to acquire only after the AGC has locked. 2 Baseband Conversion Sampling a 36 ...
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... Diversity Optimizer When two or more ZL10354s are combined in a chain using their diversity buses, the first stage chip operates in the normal way on a single tuner source, however the channel-corrected OFDM data are output to the next device in the chain. This ZL10354 combines the received diversity data with the channel-corrected data from its own OFDM demodulation process, selecting the optimum data from each source for any given carrier ...
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... MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the ZL10354 with a clock provided by the user. ...
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... OFDM data with its own received data to get the optimum reception for each carrier. The SADD1 and SADD0 pins allow up to four ZL10354s to each be defined with a different serial bus address, but the system is not limited to four devices. However, each group of (up to) four ZL10354s must be controlled via a separate serial bus to avoid address clashes ...
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... XTO 9 RESET 25 Vss 10 SLEEP 26 PLLTEST 2 Dv3 11 27 OSCMODE 3 Dv2 12 28 AVdd 13 Vdd 29 AGnd 14 Vss 30 VIN Table 3 - Pin Names Mode A - diversity first or last device in chain ZL10354 Pin Function Pin Function 33 Vdd 49 MDO0 34 RFLEV 50 MDO1 35 CLK2/GPP0 51 MDO2 36 DATA2/GPP1 52 MDO3 37 CVdd 53 MDO4 38 Vss 54 Vdd ...
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... Can be swapped with Dv4-I Pin Function Pin Function 1 Vss 17 SADD1 2 Vdd 18 SADD0 3 Vss 19 CVdd 4 CLK1 20 Vss 5 DATA1 21 PLLVdd Table 5 - Pin Names Mode C - non-diversity use ZL10354 Pin Function Pin Function 47 MOSTRT 63 MICLK 48 MOVAL 64 CVdd Pin Function Pin Function 33 Vdd 49 Dv0-O 34 RFLEV 50 Dv1-O 35 ...
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... AGnd Table 5 - Pin Names Mode C - non-diversity use (continued) In Table 6 all the possible variations are shown, of which pin numbers on the ZL10354 can be used for each of the diversity bus functions. This versatility - six different diversity pinout options - eases board layout constraints and allows the high speed diversity data buses between devices to be kept as short as possible. ...
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... Figure 7 - Basic Interconnections and Serial Address Options for Four ZL10354s on the Same Bus ...
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... VSS VSS VDD When the ZL10354 is powered up, the RESET pin 9 should be held low for at least 50 ms after VDD has reached normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0] is the R/W bit. ...
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... Write operation - as a slave receiver: S DEVICE W A RADD ADDRESS (n) Read operation - ZL10354 as a slave transmitter: S DEVICE R A DATA ADDRESS (reg 0) Write/read operation with repeated start - ZL10354 as a slave transmitter: S DEVICE W A RADD ADDRESS (n) 4.1.4 Primary 2-Wire Bus Timing t BUFF DATA1 CLK1 ...
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... Diversity Bus The diversity bus is a high speed 5-bit data bus that allows OFDM data from multiple ZL10354s to be optimized on a carrier by carrier basis. The diversity clock is output at the ADC clock rate and in the receiving device latches the data and validation bit on the rising edge. To achieve this with the optimum timing parameters, the clock should be inverted by setting the DvrClkInv bit in the DVR_CTL register (address 0x59) as part of the setup routine when using a diversity system ...
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... Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any uncorrectable packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output). ZL10354 Units Maximum 28.48 ...
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... MOSTRT MOVAL BKERR 4.3.3 MPEG Output Timing Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 85 Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -40 MOCLK frequency = 45.06 MHz. ZL10354 188 byte packet n Tp Figure 11 - MPEG Output Data Waveforms o C, Output load = 10pF Output load = 10pF. ...
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... Data output delay t 3.0 D Setup Time t 18.0 SU Hold Time t 1.0 H The hold time is better when MOCLKINV = 1, therefore this should be used if possible. MOCLK MDO } MOSTRT MOVAL BKERRB BKERR ZL10354 Units Minimum 1.0 10 Figure 12 - MPEG Timing - MOCLKINV = 1 Delay conditions Units Minimum 1 ...
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... Storage temperature Operating ambient temperature Junction temperature Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. ZL10354 Symbol Min. periphery VDD ...
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... Crystal Specification and External Clocking Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Typical load capacitance Drive level Equivalent series resistance ZL10354 Pins MDO(7:0), MOVAL, MOSTRT, MOCLK, STATUS, BKERR GPP(3:0), DATA1, AGC1, AGC2, IRQ MOSTRT, MOCLK, STATUS, BKERR ...
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... V operation - typical gm 8.736 mA/V - transconductance of amplifier at 1.8 V operation -typical Rf 2 internal feedback resistor ESR maximum equivalent series resistance of crystal - given by crystal manufacturer ( ) f fundamental frequency of crystal (Hz) ZL10354 XTI XT0 XTI C1 C2 Figure 14 - Crystal Oscillator Circuit + out ...
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... Finally the power dissipation in the crystal must be checked too high C1 and C2 must be reduced. If this is not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain condition is still satisfied. This must be done using Equation Note: 2 > > 0 ZL10354 ...
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... VCM for the differential clock signals must be 800 mV < VCM < CVDD, and the peak-to-peak signal amplitude Vpp must be >100 mV recommended that differential clock signals have VCM = 1.0V. For Vpp > 400 mV a resistor of >390 or supplied to the clock sources. ZL10354 for a clock signal switching between 0 V and and 22 k resistors) must be 800 mV < VCM < CVDD and the ...
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... Application Circuit ZL10354 Figure 16 - Typical Application Circuit 32 Zarlink Semiconductor Inc. Data Sheet ...
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