zl10354 Zarlink Semiconductor, zl10354 Datasheet - Page 23

• Manufacturer Part Number: zl10354
• Description: Diversity Enabled Nordig Unified Dvb-t Cofdm Terrestrial Demodulator For Pc-tv And Hand-held Digital Tv Dtv
• Manufacturer: Zarlink Semiconductor

4.2
The diversity bus is a high speed 5-bit data bus that allows OFDM data from multiple ZL10354s to be optimized on
a carrier by carrier basis. The diversity clock is output at the ADC clock rate and in the receiving device latches the
data and validation bit on the rising edge. To achieve this with the optimum timing parameters, the clock should be
inverted by setting the DvrClkInv bit in the DVR_CTL register (address 0x59) as part of the setup routine when
using a diversity system.
CLK clock frequency (Primary)
Bus free time between a STOP and START condition.
Hold time (repeated) START condition.
LOW period of CLK clock.
HIGH period of CLK clock.
Set-up time for a repeated START condition.
Data hold time (when input).
Data set-up time
Rise time of both CLK and DATA signals.
Fall time of both CLK and DATA signals, (100 pF to ground).
Set-up time for a STOP condition.
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
Diversity Bus
Figure 9 - Timing Diagram for the Diversity Bus with DvrClkInv = 1
Parameter
Table 7 - Timing of 2-Wire Bus
Zarlink Semiconductor Inc.
ZL10354
23
f
t
t
t
t
t
t
t
t
t
t
CLK
BUFF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
R
F
SU;STO
Symbol
1300
Min.
200
200
600
200
100
100
200
20
0
Value
note
400
Max.
1
Data Sheet
2
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit