SI4112 ETC, SI4112 Datasheet - Page 6
SI4112
Manufacturer Part Number
SI4112
Description
Dual-band RF Synthesizer WITH Integrated VCOS FOR Wireless Communications
Manufacturer
ETC
Datasheet
1.SI4112.pdf
(34 pages)
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S i4 13 3
Table 4. Serial Interface Timing
(V
6
Parameter
SCLK Cycle Time
SCLK Rise Time
SCLK Fall Time
SCLK High Time
SCLK Low Time
SDATA Setup Time to SCLK
SDATA Hold Time from SCLK
SENB to SCLK Delay Time
SCLK to SENB Delay Time
SENB to SCLK Delay Time
SENB Pulse Width
Notes:
DD
1. All timing is referenced to the 50% level of the waveforms unless otherwise noted.
2. Timing is not referenced to 50% level of the waveform. See Figure 2.
= 2.7 to 3.6 V, T
1
A
= –40 to 85°C)
2
2
2
2
S CLK
2
Figure 1. SCLK Timing Diagram
80%
50%
20%
Symbol
t
t
t
t
t
t
hold
en1
en2
en3
t
t
clk
t
t
t
su
w
h
r
f
l
t
Rev. 1.1
r
Test Condition
t
h
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
t
t
clk
f
t
l
Min
40
10
10
10
12
12
10
—
—
5
0
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
50
50
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns