nm34c02 Fairchild Semiconductor, nm34c02 Datasheet
nm34c02
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nm34c02 Summary of contents
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... This will enable "plug and play" capability as the module is read and PC main memory resources utilized through the memory controller. The first 128 bytes of the memory of the NM34C02 can be permanently Write Protected by writing to the "WRITE PROTECT" Register. Write Protect implementation details are described under the section titled Addressing the WP Register ...
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... Connection Diagram Ordering Information NM34C02 NM34C02 Rev. D.2 SO (M8) and TSSOP (MT8) Package NM34C02 SCL SDA DS012821-2 Top View See Package Number M08A and MTC08 Pin Names A0,A1,A2 Device Address Inputs V Ground SS SDA Data I/O SCL ...
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... Input/Output Capacitance (SDA) I/O C Input Capacitance (A0, A1, A2, SCL) IN Note 1: Typical values are and nominal supply voltage (5V). A Note 2: This parameter is periodically sampled and not 100% tested. NM34C02 Rev. D.2 Operating Conditions Ambient Operating Temperature – +150 C NM34C02 NM34C02E 6.5V to –0.3V Positive Power Supply NM34C02 ...
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... During the write cycle, the WR NM34C02 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. NM34C02 Rev. D ...
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... The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state recommended that the total line capacitance be less than 400pF. Specific timing and addressing considerations are described in greater detail in the following sections. NM34C02 Rev. D HIGH ...
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... Stop Condition All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM34C02 to place the device in the standby power mode ...
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... Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier ( see Figure 4) . This is fixed as 1010 for all EEPROM devices. NM34C02 Rev. D.2 8th BIT ACK t WR ...
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... ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM34C02 is still busy with the write operation no ACK will be returned. If the NM34C02 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation ...
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... R/W bit set to one. This will be followed by an acknowl- edge from the NM34C02 and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM34C02 discontinues trans- mission ...
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... After the entire memory has been read, the counter 'rolls over' and the NM34C02 continues to output data for each acknowledge re- ceived. Refer to Figure 10 for the address, acknowledge, and data transfer sequence. ...
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... Max, Typ. All leads 0.014 0.016 - 0.050 (0.356) (0.406 - 1.270) 0.050 Typ. All Leads (1.270) Typ Order Number NM34C02LM8/LZM8 Package Number M08A 11 0.189 - 0.197 (4.800 - 5.004 0.004 - 0.010 (0.102 - 0.254) Seating Plane 0.014 - 0.020 Typ ...
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... DETAIL A Typ. Scale: 40X 0.020 - 0.028 (0.50 - 0.70) 8-Pin Molded TSSOP, JEDEC (MT8) Order Number NM34C02LMT8/LZMT8 Package Number MTC08 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system affect its safety or effectiveness ...