nm34c02 Fairchild Semiconductor, nm34c02 Datasheet - Page 9

• Manufacturer Part Number: nm34c02
• Description: 2k-bit Standard 2-wire Bus Interface
• Manufacturer: Fairchild Semiconductor

NM34C02 Rev. D.2
Write Protect Scheme
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to a one. There are three basic read operations: current
address read, random read, and sequential read.
CURRENT ADDRESS READ
Internally the NM34C02 contains an address counter that main-
tains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to one, the
NM34C02 issues an acknowledge and transmits the data byte.
The master will not acknowledge the transfer but does generate
a stop condition, and therefore the NM34C02 discontinues trans-
mission. Refer to Figure 8 for the sequence of address, acknowl-
edge and data transfer.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
Bus Activity:
SDA Line
Master
S
A
R
T
T
Bus Activity:
Master
SDA Line
Bus Activity:
Bus Activity:
ADDRESS
SDA Line
SLAVE
Master
(Continued)
R
S
T
A
T
S
A
R
T
T
C
A
K
ADDRESS
DEVICE
BYTE ADDRESS (n)
ADDRESS
ADDRESS
SLAVE
WP Register Write (Figure 7).
SLAVE
Page Write (Figure 6).
Byte Write (Figure 5).
C
A
K
C
A
K
A
C
K
DON'T CARE
9
ADDRESS
ADDRESS
BYTE
WORD
slave address, R/W bit set to zero, and then the word address to
be read. After the Slave word address acknowledge, the master
immediately reissues the start condition and the slave address
with the R/W bit set to one. This will be followed by an acknowl-
edge from the NM34C02 and then by the eight bit word. The
master will not acknowledge the transfer but does generate the
stop condition, and therefore the NM34C02 discontinues trans-
mission. Refer to Figure 9 for the address, acknowledge and data
transfer sequence.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM34C02 continues to output data for each acknowl-
edge received. The read operation is terminated by the master not
responding with an acknowledge or by generating a stop condi-
tion.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
DATA n
A
C
K
A
C
K
A
C
K
DON'T CARE
DATA
DATA
DATA n + 1
C
A
K
A
C
K
A
C
K
S
O
P
T
O
S
T
P
DATA n + 15
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C
A
K
O
S
T
P