act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 11

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

Primary I
Primary D
Secondary ECC[25]
Cache Locking
fragments to be locked into the primary and secondary
caches. The user has complete control over what locking is
performed with cache line granularity. For instruction and
data fragments in the primaries, locking is accomplished by
setting either or both of the cache lock enable bits in the
CP0 ECC register, specifying the set via a field in the CP0
ECC register, and then executing either a load instruction
or a Fill_I cache operation for data or instructions
respectively. Only two sets are lockable within each cache:
set A and set B. Locking within the secondary works
identically to the primaries using a separate secondary lock
enable bit and the same set selection field. As with the
primaries, only two sets are lockable: sets A and B. Table 7
summarizes the cache locking capabilities.
Cache Management
operations
ACT 7000ASC significantly improves the speed of
operation of certain critical cache management operations
as compared with the R5000 and R4000 families. In
particular, the speed of the Hit-Write-back-Invalidate and
Hit-Invalidate cache operations has been improved in some
cases by an order of magnitude over that of the earlier
families. Table 8 compares the ACT 7000ASC with the
R4000 and R5000 processors.
Index
Tag
Write policy
read policy
read order
write order
miss restart following:
Parity
Cache
The ACT 7000ASC allows critical code or data
To improve the performance of critical data movement
SCD7000A Rev B
Table 7 – Cache Locking Control
Attribute
ECC[27]
ECC[26]
in
Enable
Lock
the
ECC[28]=0
ECC[28]=1
ECC[28]=0
ECC[28]=1
ECC[28]=0
ECC[28]=1
embedded
Set Select
vAddr
pAddr
n.a.
critical word first
NA
complete line
n.a.
per word
11..0
35..12
→
→
→
→
→
→
A
B
A
B
A
B
environment,
Instruction
Table 6 – Cache Attributes (cont)
Fill_I
Load/Store
Fill_I or
Load/Store
Activate
the
11
vAddr
pAddr
write-back, write-through
non-blocking (2 outstanding) non-blocking (data only, 2
critical word first
sequential
first double (if waiting for
data)
per byte
Hit-Writeback-
Invalidate
Hit-Invalidate
writeback buffer is full from some previous cache eviction
then n is the number of cycles required to empty the
write-back buffer. If the buffer is empty then n is zero.
beyond the one cycle required to issue the instruction that
is required to implement the operation.
Primary Write Buffer
cache miss write-backs or stores to uncached or
write-through addresses, use the integrated primary write
buffer. The write buffer holds up to four 64-bit address and
data pairs. The entire buffer is used for a data cache
write-back and allows the processor to proceed in parallel
with memory update. For uncached and write-through
stores, the write buffer significantly increases performance
by decoupling the SysAD bus transfers from the instruction
execution stream.
System Interface
system interface which is compatible with the RM5200
Family and R5000. Unlike the R4000 and R5000 family
processors which provide only an integral multiplication
Operation
For the Hit-Dirty case of Hit-Writeback-Invalidate, if the
The penalty value is the number of processor cycles
Writes to secondary cache or external memory, whether
The ACT 7000ASC provides a high-performance 64-bit
11..0
35..12
Data
Table 8 – Penalty Cycle
Condition
Hit-Clean
Hit-Dirty
Miss
Miss
Hit
pAddr
outstanding)
critical word first
sequential
n.a.
per doubleword
pAddr
ACT 7000ASC R4000/R5000
block write-back, bypass
3+n
35..16
15..0
0
3
0
2
Secondary
Penalty
14+n
12
7
9
7