cl-ps6700 Cirrus Logic, Inc., cl-ps6700 Datasheet - Page 11

• Manufacturer Part Number: cl-ps6700
• Description: Low-power Pc Card Controller For The Cl-ps7111
• Manufacturer: Cirrus Logic, Inc.

CL-PS6700
Low-Power PC Card Controller
2.1.1 Address/Data Bus Signals
Signal Type
MD[15:0]
(cont.)
November 1997
I/O
Source
Power
sys
PRELIMINARY DATA BOOK v1.0
Description
Data Phase: If a write transfer is indicated (during the address phase), write data appears in the
third clock (also a word write, during the fourth clock) of Chip Enable. For register read transfers, a
two-clock data phase follows the two clocks of address phase after a one clock bus turnaround
cycle. For card reads, the data phase is deferred until card data has been collected as signaled by
PRDY; the data phase is initiated by a second assertion of PCE_L, and the CL-PS6700 drives this
bus with read data in the clock following the assertion of PCE_L (if a word read, during the second
clock following PCE_L).
The data phase of MD[15:0] carries the transfer size and space required for the data (see
and
C
Table 2-2.
I R R U S
SIZE[1:0]
Table
00
11
2-3). SLOT[1:0] is a space reserved for future expansion.
L
Transfer Size
O G I C
(cont.)
Number of bytes
C
MD[15]
MD[15]
O N F I D E N T I A L
SIZE[1:0]
1
4
SLOT[1:0]
1st Clock of Address Phase
2nd Clock of Address Phase
, N D A R
SPACE[1:0]
A[15:0]
Table 2-3. Area Accessed
SPACE[1:0]
00
01
10
11
E Q U I R E D
A[25:16]
Area Accessed
Attribute space
I/O space
Common memory
CL-PS6700 register
space
MD[0]
MD[0]
PIN DESCRIPTIONS
Table 2-2
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