k9k1g08q0a Samsung Semiconductor, Inc., k9k1g08q0a Datasheet - Page 8

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k9k1g08q0a

Manufacturer Part Number
k9k1g08q0a
Description
128m X 8 Bit / 64m X 16 Bit Nand Flash Memory
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
Figure 1-2. K9K1G16X0A (X16) FUNCTIONAL BLOCK DIAGRAM
Figure 2-2. K9K1G16X0A (X16) ARRAY ORGANIZATION
K9K1G08Q0A
K9K1G08U0A
NOTE : Column Address : Starting Address of the Register.
V
V
(=8192 Blocks)
2nd Cycle
3rd Cycle
CC
1st Cycle
4th Cycle
SS
256K Pages
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
CE
RE
WE
Command
A
A
I/O 0
A
A
9
A
A
0
17
25
K9K1G16Q0A
K9K1G16U0A
- A
0
9
- A
25
7
I/O 1
A
A
A
A
10
18
26
1
(=256 Words)
Page Register
& High Voltage
CLE ALE
Page Register
Control Logic
256Word
256 Word
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Generator
Register
I/O 2
A
A
A
L*
11
19
2
WP
I/O 3
A
A
A
L*
12
20
3
8 Word
8 Word
I/O 4
A
A
A
L*
13
21
4
8
I/O 5
A
A
A
L*
I/O 0 ~ I/O 15
14
22
5
Global Buffers
(256 + 8)Word x 262144
Page Register & S/A
I/O Buffers & Latches
I/O 6
512M + 16M Bit
A
A
A
L*
NAND Flash
15
23
16 bit
6
Y-Gating
ARRAY
1 Block =32 Pages
= (8K + 256) Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
1 Device = 264Words x 32Pages x 8192 Blocks
I/O 7
A
A
A
L*
16
24
7
= (8K + 256) Word
= 1056 Mbits
I/O8 to 15
FLASH MEMORY
L*
L*
L*
L*
Output
Driver
Column Address
Row Address
(Page Address)
Preliminary
V
V
CC/
SS
I/0 0
I/0 15
Vcc
Q

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