lp62s1024ax-70llt AMIC Technology Corporation, lp62s1024ax-70llt Datasheet - Page 10

• Manufacturer Part Number: lp62s1024ax-70llt
• Description: 128k Voltage Cmos Sram
• Manufacturer: AMIC Technology Corporation

Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
Notes: 1. t
(August, 2001, Version 1.0)
2. A Write occurs during the overlap (t
3. t
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
5. t
6. OE is continuously low. ( OE = V
7. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
Address
D
CE1
CE2
the WE transition, outputs remain in a high impedance state.
WE
AS
WR
CW
D
OUT
IN
is measured from the address valid to the beginning of Write.
is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
is measured from the later of CE1 going low or CE2 going high to the end of Write.
t
AS
1
IL
)
WP
(4)
(4)
) of a low CE1, a high CE2 and a low WE .
t
AW
t
t
t
CW 5
WP
CW 5
t
WC
t
10
2
WHZ
7
t
DW
t
WR 3
LP62S1024A-T Series
t
DH
AMIC Technology, Inc.