bt848kpf ETC-unknow, bt848kpf Datasheet - Page 116

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

C
ADC Interface Register
ADC Interface Register
Memory Mapped Location 0x068 – (ADC)
Upon reset, it is initialized to 0x82. CRUSH is the least significant bit.
106
Bits
ONTROL
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
R
EGISTER
Type
RW
RW
RW
RW
RW
RW
RW
D
Default
10
0
0
0
0
1
0
EFINITIONS
Name
Reserved
SYNC_T
SYNC_T
AGC_EN
CLK_SLEEP
Y_SLEEP
C_SLEEP
CRUSH
Description
These bits should only be written with logical one and logical zero.
This bit defines the voltage level below which the SYNC signal can
be detected.
This bit is reserved in the Bt848A and Bt849A and must be set to
zero.
This bit controls the AGC function. If disabled REFOUT is not
driven and an external reference voltage must be provided. If
enabled, REFOUT is driven to control the A/D reference voltage.
When this bit is at a logical one, the decoder clock is powered
down, but the device registers are still accessible. Recovery time is
approximately one second to return to capturing video.
This bit enables putting the luma ADC in sleep mode.
This bit enables putting the chroma ADC in sleep mode.
When the CRUSH bit is high (adaptive AGC), the gain control
mechanism monitors the A/D’s for overflow conditions. If an over-
flow is detected, the REFOUT voltage is increased, which
increases the input voltage range on the A/D’s.
0
1
0
1
0
1
0
1
0
1
0
1
L848A_A
= Analog SYNCDET threshold high (~125 mV)
= Analog SYNCDET threshold low (~75 mV)
= AGC Enabled
= AGC Disabled
= Normal Clock Operation
= Shut down the System Clock (Power Down)
= Normal Y ADC operation
= Sleep Y ADC operation
= Normal C ADC operation
= Sleep C ADC operation
= Non-adaptive AGC
= Adaptive AGC
Single-Chip Video Capture for PCI
Bt848/848A/849A
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