bt848kpf ETC-unknow, bt848kpf Datasheet - Page 76

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

E
PCI Bus Interface
66
LECTRICAL
I
NTERFACES
PCI Bus Interface
The PCI local bus is an architectural, timing, electrical, and physical interface that
allows the Bt848 to interface to the local bus of a host CPU. Bt848 is fully com-
pliant with PCI Rev. 2.1 specifications.
The supported bus cycles for the PCI target only are as follows:
Memory Read Multiple and Memory Read Line are treated in the same manner as
Memory Read.
driven if GNT is asserted and follows an idle cycle (regardless of the state of BUS
MASTER).
clock cycles. This allows for a full internal clock cycle address decode time (me-
dium devsel timing) and a registered state machine interface. Write burst transac-
tions can continue with zero wait state performance on the fourth clock cycle and
onward (unless writing to video decoder/scaler registers). All read burst transac-
tions contain 1 wait-state per data phase. A block diagram of the PCI interface is
shown in Figure 28.
The supported bus cycles for the PCI initiator and target are as follows:
Memory Write and Invalidate is treated in the same manner as Memory Write.
The unsupported PCI bus features are as follows:
As a PCI master, Bt848 supports agent parking, AD[31:0], CBE[3:0], and PAR
All bus commands accepted by the Bt848 as a target require a minimum of 3
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Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
64-bit Bus Extension
I/O Transactions
Special, Interrupt Acknowledge, Dual Address Cycles
Locked Transactions
Caching Protocol
Initiator Fast Back-to-back Transactions to Different Targets
L848A_A
Single-Chip Video Capture for PCI
Bt848/848A/849A
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