mu9c4320l-90tdi Music Semiconductors, Inc., mu9c4320l-90tdi Datasheet - Page 10

• Manufacturer Part Number: mu9c4320l-90tdi
• Description: Mu9c4320l Atmcam
• Manufacturer: Music Semiconductors, Inc.

individual bits in the VP Table are set and reset through
control states. A LOW value in the VP Table indicates a
match, while a HIGH value indicates a mismatch. The
results of comparison in the CAM array have a higher
priority than the VP Table result. In other words, if there is
a match in the CAM array, the VP Table result is ignored,
and the match is flagged by /MV and /MF going LOW. If
there is a mismatch in the CAM array, then a VP Table
match is indicated by /MV going LOW and /MF
remaining HIGH. In the event of a mismatch in both the
CAM array and the VP Table, both /MV and /MF remain
HIGH. The following truth table shows how match
conditions are flagged:
Note: The /MV line will be LOW in any device with a match,
regardless of its priority. Only when the /MV line is LOW and the
/MF line is HIGH in the lowest-priority device will there be a VP
Table match and no CAM array match.
The VPI field can be masked through the Configuration
register. The VPI values are ANDed with the VP Table
Address Mask bit; therefore, “zeros” can be forced into
any of the VP Table Address bits. This facility is useful in
cases where the VPI values are coded on less than 12 bits.
For example, for 8-bit VPI processing, the Table Address
Mask field would have “zeros” in the upper-order four bits
and “ones” in the rest. This masked address is the value
output on the AA11–0 bus while the VP Page address is
output on the PA3–0 bus during a VP Table match. Note
that the VP Table Address Mask bits are only active for
Comparison cycles, and not for other VP Table accesses.
MU9C4320L ATMCAM
/MV
0
0
1
1
/MF Compare Cycle Result
0
1
0
1
Match in CAM
Match in VP Table
/MI = LOW (CAM match in higher priority device)
No Match
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The ATMCAM supports JTAG boundary-scan testing
through the pins TCK, TMS, TDI, and TDO, according to
the IEEE 1149 Standard: Test Access Port and
Boundary-scan Architecture. The following JTAG support
is provided: BYPASS, SAMPLE/PRELOAD, IDCODE,
CLAMP, INTEST, and EXTEST. Signals on input pins can
be captured and signals on output pins can be driven,
allowing testing of board-level interconnection and
internal device testing.
Hardware Control
Performance of the ATMCAM is enhanced by direct
hardware control through a set of control states through
the AC11–0 lines. The Hardware Control mode is selected
when Configuration Register bits FR27–26 are set LOW.
The AC11–0 inputs are qualified by the /W, /AV, and /VB.
When /AV is LOW, the AC11–0 lines carry the address for
a random Read or Write cycle, depending on the state of
/W, and /VB carries the validity of the location. During a
Write cycle, /VB is written to the Validity bit of the
addressed location; during a Read cycle, the validity of the
location is read on the /VB line. When /VB is LOW, the
location contains valid data; when /VB is HIGH the
location is empty.
When /AV is HIGH, the AC11–0 lines carry address and
control information. The control information is conveyed
on AC8–0. If masking is not used, and all random
addressing of the memory is indirect through the Address
register, then only the AC5–0 lines are needed for full
control of the device.
In applications where a restricted number of control lines
are available, or where speed is not critical, the ATMCAM
can be controlled in Software Control mode where the
control states are loaded into the Instruction register
through the DQ31–0 lines. The control states are identical
in both Hardware and Software Control modes, although
DQ12 takes on special significance in Software mode.
Operational Characteristics
Rev. 3