mu9c4320l-90tdi Music Semiconductors, Inc., mu9c4320l-90tdi Datasheet - Page 12

• Manufacturer Part Number: mu9c4320l-90tdi
• Description: Mu9c4320l Atmcam
• Manufacturer: Music Semiconductors, Inc.

PA3–0:AA11–0 After a Write at Next Free Address
Cycle
After a Write at Next Free Address cycle the
PA3–0:AA11–0 lines carry the address that was written to
during that cycle. Only the device in which the write
occurred enables its PA3–0:AA11–0 lines. All other
devices keep their PA3–0:AA11–0 lines in high
impedance regardless of the state of their /OE inputs.
In the event that the system was full prior to the Write at
Next Free Address cycle being executed, so that the write
operation was suppressed, the PA3–0:AA11–0 lines carry
all 1s. The lowest-priority device, as indicated by bit FR25
in the Configuration register, enables its PA3–0:AA11–0
lines and provides the source of all 1s. All other devices
keep their PA3–0:AA11–0 lines in high impedance
regardless of the state of their /OE inputs.
PA3–0:AA11–0 After a Random Access Read or Write
to the CAM
After a random Read or Write cycle to the CAM, the
PA3–0:AA11–0 lines carry the address that was accessed
during that cycle. Only the device in which the access
occurred enables its PA3–0:AA11–0 lines. All other
devices keep their PA3–0:AA11–0 lines in high
impedance regardless of the state of their /OE inputs. Note
that the access to the PA3–0:AA11–0 bus differs in this
respect from the operation of the Status register which is
accessible in any selected device under this particular
circumstance.
In the event that the Write cycle was broadcast to multiple
devices, all devices that have their /OE lines held LOW
will enable their PA3–0:AA11–0 lines. Under this
circumstance, it is up to the system designer to ensure that
only one /OE line is driven LOW to prevent bus
contention on the PA3–0:AA11–0 lines.
PA3–0:AA11–0 After a Random Access Read or Write
to the VP Table
After a Read or Write cycle to the VP Table, the
PA3–0:AA11–0 lines carry the address of the location
accessed in the VP Table. The VP Table is held in the
lowest-priority device, which therefore is the only device
to enable its PA3–0:AA11–0 lines. All other devices keep
their PA3–0:AA11–0 lines in high impedance regardless
of the state of their /OE inputs.
MU9C4320L ATMCAM
12
PA3–0:AA11–0 Conditions of Operation
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PA3–0:AA11–0 and the Match Flags
The Match flags /MV, /MF, /MM reflect the results of the
most recent Comparison cycle. During a Comparison
cycle, they do not change until after /E has gone HIGH
after which they are free to change combinatorially; their
state is not latched when /E is LOW. This condition allows
some pipelining to occur and is useful in systems with
long daisy chains. A Comparison cycle can be followed by
another cycle that does not affect the PA3–0:AA11–0 lines
before the daisy chain is resolved. For example:
The WR CR control state can be executed before the daisy
chain has resolved device prioritization after the CMP CR
control state. The /OE is then asserted at a suitable time,
depending on the length of the daisy chain. The Match
address of the highest-priority responding device is then
driven onto the PA3–0:AA11–0 lines.
The /MV, /MF, /MM lines continue to indicate the results
of the most recent match, even when the PA3–0:AA11–0
lines carry an address other than the Match address. This
condition allows rapid return to the Match address value
on the PA3–0:AA11–0 lines through a RD[HPM] cycle,
without the daisy chain having to re-resolve device-level
prioritization.
During a control state that does not have any effect on
the device address, such as a Write Register cycle, the
PA3–0:AA11–0 lines remain unchanged. In other
words, the state of the PA3–0:AA11–0 lines persists
until another cycle causes it to change.
When
PA3–0:AA11–0 lines are only free to change while /E
is HIGH. When /E goes LOW the PA3–0:AA11–0
lines are latched.
The PA3–0:AA11–0 lines are enabled when /OE is
LOW provided that the previous cycle causes them to
be active. When /OE is HIGH, the PA3–0:AA11–0
lines are in high impedance. Note that /OE is
asynchronous with respect to /E, and is independent
of Chip Select from either /CS1, /CS2, or through the
Device Select register, except in the case of
non-broadcast random Read and Write cycles to the
CAM.
enabled
CMP CR
WR CR
by
Operational Characteristics
/OE
being
LOW,
Rev. 3
the