sh6612a SinoWealth Micro-Electronics Corp. Ltd, sh6612a Datasheet - Page 6

• Manufacturer Part Number: sh6612a
• Description: 2k 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

5. Timer0 & Timer1
SH6612A has two 8-bit timers.
The timer / counter has the following features:
- 8-bit up-counting timer/counter.
- Automatic re-loads counter.
- 8-level prescaler.
- Interrupt on overflow from $FF to $00.
The following is a simplified timer block diagram.
The timers provide the following functions:
- Programmable interval timer function.
- Read counter value.
(a) Timer0 and Timer1 Configuration and Operation
Both the Timer0 and Timer1 consist of an 8-bit write-only
timer load register (TL0L, TL0H; TL1L, TL1H) and an 8-bit
read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each
of them has low order digits and high order digits. Writing
data into the timer load register (TL0L, TL0H; TL1L, TL1H)
can initialize the timer counter.
(b) Timer Mode Register
The timer can be programmed in several different prescaler ratios by setting Timer Mode register (TM0, TM1).
The 8-bit counter prescaler overflow output pulses. The Timer Mode registers (TM0, TM1) are 3-bit registers used for the
timer control as shown in Table 1 and Table 2. These mode registers select the input pulse sources into the timer.
Table 1: Timer0 Mode Register ($02)
TM0.2 TM0.1 TM0.0
0
0
0
0
1
1
1
1
Fosc/4
0
0
1
1
0
0
1
1
TM.2
PRESCALER
Tosc
TM.1
0
1
0
1
0
1
0
1
TM.0
Divide Ratio
Prescaler
SYNC
/2
/2
/2
/2
/2
/2
/2
/2
11
9
7
5
3
2
1
0
COUNTER
8-BIT
Clock Source
System clock
System clock
System clock
System clock
System clock
System clock
System clock
System clock
6/24
The low-order digit should be written first, and then the
high-order digit. The timer counter is automatically loaded
with the contents of the load register when the high order
digit is written or counter counts overflow from $FF to $00.
Timer Load Register: Since the register H controls the
physical READ and WRITE operations. Please follow
these steps:
Write Operation:
Read Operation:
Table 2: Timer1 Mode Register ($03)
TM1.2 TM1.1 TM1.0
0
0
0
0
1
1
1
1
Load Reg. L
Latch Reg. L
Low nibble first
High nibble to update the counter
High Nibble first
Low nibble followed.
0
0
1
1
0
0
1
1
8-bit timer counter
0
1
0
1
0
1
0
1
Load Reg. H
Divide Ratio
Prescaler
/2
/2
/2
/2
/2
/2
/2
/2
11
9
7
5
3
2
1
0
Clock Source
System clock
System clock
System clock
System clock
System clock
System clock
System clock
System clock
SH6612A
Ver 0.3