sh66l16a SinoWealth Micro-Electronics Corp. Ltd, sh66l16a Datasheet - Page 17

• Manufacturer Part Number: sh66l16a
• Description: 16k 4-bit Low Power Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

10. Interrupt
Four interrupt sources are available on SH66L16A:
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program.
Those flags are cleared to “0” at initialization by the chip reset.
System Register:
When IEx is set to “1” and the interrupt request is generated (IRQx is “1”), the interrupt will be activated and vector address will
be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are cleared to “0” automatically, so when IRQx is “1” and IEx is set to “1” again, the interrupt will be activated and vector address
will be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Nesting
During the CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing
sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the
instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions.
However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be
terminated.
External Interrupt
When Bit3 of system register $00 (IEX) is set to “1”, the external interrupt will be enabled, and a low level applying on the
external interrupt I/O port will generate an external interrupt. External Interrupt can be used to wake the CPU from HALT or
STOP mode.
Timer Interrupt
The input clock of Timer0 is based on the system clock. The timer overflow from $FF to $00 will generate an internal interrupt
request (IRQT0 = 1). If the interrupt enable flag is enabled (IET0 = 1), a timer interrupt service routine will start. Timer interrupt
can also be used to wake the CPU from HALT mode.
Base Timer Interrupt
The Base Timer is based on OSC or OSCX clock. The timer overflow from $FF to $00 will generate an internal interrupt request
(IRQBT = 1). If the interrupt enable flag is enabled (IEBT = 1), a timer interrupt service routine will start. Base Timer interrupt can
also be used to wake the CPU from HALT or STOP mode.
Port Low Active Interrupt
Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request.
Any one of the I/O input port applying with a low level would generate an interrupt request (IRQP = 1). In order to avoid
multi-responses, it is strongly recommended that the relative input port cannot be connected with a low level all the time. Port
Interrupt can be used to wake the CPU from HALT or STOP mode.
- External interrupt (INT0 share with PORTA.0)
- Timer0 interrupt
- Base Timer interrupt
- PORTB & PORTC interrupts (Low active)
Address
$00
$01
Inst.cycle
IRQX
Bit 3
IEX
Interrupt Generated
IRQT0
Bit 2
IET0
Instruction
Execution
1
N
IRQBT
IEBT
Bit 1
Interrupt Servicing Sequence Diagram
Interrupt Accepted
Instruction
Execution
2
I1
IRQP
Bit 0
IEP
17
R/W
R/W
R/W
Vector Generated
Instruction
Execution
Stacking
3
I2
Interrupt enable flags register
Interrupt request flags register
Fetch Vector address
Reset IE.X
4
Remarks
Start at vector address
5
SH66L16A