ch7028b Chrontel, ch7028b Datasheet - Page 11

• Manufacturer Part Number: ch7028b
• Description: Chrontel Ch7028b Sdtv Encoder
• Manufacturer: Chrontel

CHRONTEL
2.0 Functional Description
2.1
2.1.1 Overview
Five distinct methods of transferring data to the CH7028B are described below.
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7028B is latched with both edges of the
clock (also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X or 3X pixel rate the
data applied to the CH7028B is latched with one edge of the clock (also known as single edge transfer mode or SDR).
For the unitary data, clock at 1X pixel rate, the data applied to the CH7028B is latched with one edge of the clock. The
polarity of the pixel clock can be reversed under serial port control. Hsync and Vsync can be input individually or
embedded into data signal such as BT656 input format.
2.1.2 Input Clock and Data Timing Diagram
Figure 3 to Figure 6 below shows the timing diagram for input data and clocks. The timing requirements are given in
later section.
(Note: In Figure 3, the first XCLK waveform represents the input clock for single edge transfer (SDR) methods. The
second XCLK waveform represents the input clock for the dual edge transfer (DDR) method.)
209-1000-001
1. Unitary data, clock input at 1X the pixel rate (SDR mode)
2. Multiplexed data, clock input at 1X of pixel rate (DDR mode)
3. Multiplexed data, clock input at 2X of pixel rate
4. Multiplexed data, clock input at 3X of pixel rate
5. 16 bit CPU/MEMERY interface
Data
Data
Xclk
Hsync
DE
Xclk
Xclk
(1x)
(1x)
(2x)
Input Interface
P0a
HW
One Pixel
Rev. 1.1,
P0b
P1a
08/21/2008
Figure 4: SDR and DDR Input Data Formats
P1b
Figure 5: Horizontal Input Timing
P2a
P2b
HT
HA
…
Pna
Pnb
…
HO
CH7028B
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