ch7028b Chrontel, ch7028b Datasheet - Page 7

• Manufacturer Part Number: ch7028b
• Description: Chrontel Ch7028b Sdtv Encoder
• Manufacturer: Chrontel

CHRONTEL
1.2
Table 1: Pin Name Description (BGA Package)
Pin #
A5, D4, F7, E9,
D5, D6, A7, E6,
B7, A8, F6, B8,
B9, C9, C8, D9,
D8, E8
C2
B3
A2
D2
F5
C1
K9
L9
L4
L3
L5
209-1000-001
Pin Description
Rev. 1.1,
Type
In
In/Out
In/Out
In
In
In
In
In/Out
In
Out
Out
In
08/21/2008
Symbol
D[17:0]
V
H/WEB
DE/CSB
AS
ATPG
RESETB
SPD
SPC
DAC0
DAC1
ISET
[1]
Description
Data[0] through Data[17] Inputs
These pins accept the 18 data inputs from a digital video port
of a graphics controller. The swing is defined by VDDIO.
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical
sync input for use with the input data.
When the SYO control bit is high, the device will output a
vertical sync pulse. The output is driven from the VDDIO
supply.
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a
horizontal sync input for use with the input data.
When the SYO control bit is high, the device will output a
horizontal sync pulse. The output is driven from the VDDIO
supply.
It is also the WEB signal of CPU/MEMORY interface.
Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
It is also the CSB signal of CPU/MEMORY interface.
Serial Port Device Address Select
0: 76h
1: 75h
ATPG Enable (Internally pull-low)
This pin should be left open or pulled low with a 10k resistor
in the application. This pin configures the pre-condition for
scan chain and boundary scan test when high. Otherwise it
should be pulled low. Voltage level is 0 to 3.3V.
Active low reset.
When RESETB is low, the device is held in the hardware
reset condition. When RESETB is high, reset is controlled
through the serial port.
Serial Port Data Input / Output (open drain)
This pin functions as the bi-directional data pin of the serial
port. External pull-up resistor is required.
Serial Port Clock Input (open drain)
This pin functions as the clock pin of the serial port. External
pull-up resistor is required.
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3 V.
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3 V.
Current Set
This pin sets the DAC current. A 1.2k Ω, 1% tolerance
resistor should be connected between this pin and
AGND_DAC using short and wide trace.
CH7028B
7