ch7013a Chrontel, ch7013a Datasheet

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... Rev. 1.5, 9/1/2004 Digital Encoder 2. G ENERAL Chrontel’s CH7013A digital encoder is a stand- alone integrated circuit providing a robust solution for TV output. It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format. † ...

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... Package Diagram 1 D[3] D[3] 2 D[4] D[4] 3 D[5] D[5] 4 D[6] D[6] 5 DVDD DVDD 6 D[7] D[7] 7 D[8] D[8] 8 DGND] DGND] 9 D[9] D[9] 10 D[10] D[10] 11 D[11] D[11] 2 CHRONTEL CH7013A Figure 2: 44-PIN TQFP (1.4 mm) CH7013A 33 XO/FIN XO/FIN AVDD 31 AVDD DVDD 30 DVDD ADDR 29 ADDR DGND 28 DGND CLOCK 27 SC DATA 26 SD VDD 25 VDD RSET 24 RSET GND 23 GND 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P- OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7013A accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum ...

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... Analog ground These pins provide the ground reference for the analog section of the CH7013A, and MUST be connected to the system ground, to prevent latchup. Refer to the Application Information section for information on proper supply de-coupling. Analog Supply Voltage These pins supply the 5V power to the analog section of the CH7013A ...

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... Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7013A. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first value of the (Total Pixels/Line x Total Lines/Frame) column of the Table 17 on page 25 (display Mode Register OOH description) ...

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... Y0[7] R1[3] R2[4] R3[4] Y0[6] R1[2] R2[3] R3[3] Y0[5] R1[1] R2[2] R3[2] Y0[4] R1[0] R2[1] R3[1] Y0[3] G1[5] R2[0] R3[0] Y0[2] G1[4] G2[4] G3[4] Y0[1] G1[3] G2[3] G3[3] Y0[0] G1[2] G2[2] G3[2] Cb0[7] G1[1] G2[1] G3[1] Cb0[6] G1[0] G2[0] G3[0] Cb0[5] B1[4] B2[4] B3[4] Cb0[4] B1[3] B2[3] B3[3] Cb0[3] B1[2] B2[2] B3[2] Cb0[2] B1[1] B2[1] B3[1] Cb0[1] B1[0] B2[0] B3[0] Cb0[0] CH7013A HP1 HP P1a P1b P2a P2b YCrCb (16-bit Y1[7] Y2[7] Y3[7] Y1[6] Y2[6] Y3[6] Y1[5] Y2[5] Y3[5] Y1[4] Y2[4] Y3[4] Y1[3] Y2[3] Y3[3] Y1[2] Y2[2] Y3[2] Y1[1] Y2[1] Y3[1] Y1[0] Y2[0] Y3[0] Cr0[7] Cb2[7] Cr2[7] Cr0[6] Cb2[6] Cr2[6] Cr0[5] Cb2[5] Cr2[5] Cr0[4] Cb2[4] Cr2[4] Cr0[3] Cb2[3] Cr2[3] Cr0[2] Cb2[2] Cr2[2] ...

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... Y2[2] S[1] Y0[1] Y1[1] Y2[1] S[0] Y0[0] Y1[0] Y2[0] 0 Cb0[7] Cr0[7] Cb2[7] 0 Cb0[6] Cr0[6] Cb2[6] 0 Cb0[5] Cr0[5] Cb2[5] 0 Cb0[4] Cr0[4] Cb2[4] 0 Cb0[3] Cr0[3] Cb2[3] 0 Cb0[2] Cr0[2] Cb2[2] 0 Cb0[1] Cr0[1] Cb2[1] 0 Cb0[0] Cr0[0] Cb2[0] CH7013A Y3[7] Y4[7] Y5[7] Y3[6] Y4[6] Y5[6] Y3[5] Y4[5] Y5[5] Y3[4] Y4[4] Y5[4] Y3[3] Y4[3] Y5[3] Y3[2] Y4[2] Y5[2] Y3[1] Y4[1] Y5[1] Y3[0] Y4[0] Y5[0] Cr2[7] Cb4[7] Cr4[7] Cr2[6] Cb4[6] Cr4[6] Cr2[5] Cb4[5] Cr4[5] Cr2[4] Cb4[4] Cr4[4] Cr2[3] Cb4[3] ...

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... P2 t SP2 P0a P0b 7 RGB 5-6-5 P0b P1a P1b P0a R0[4] G1[2] R1[4] G0[2] R0[3] G1[1] R1[3] G0[1] R0[2] G1[0] R1[2] G0[0] R0[1] B1[4] R1[1] B0[4] R0[0] B1[3] R1[0] B0[3] G0[5] B1[2] G1[5] B0[2] G0[4] B1[1] G1[4] B0[1] G0[3] B1[0] G1[3] B0[0] 4 12-bit RGB (12-12) P0b P1a P1b P0a R0[7] G1[3] R1[7] G0[4] R0[6] G1[2] R1[6] G0[3] R0[5] G1[1] R1[5] G0[2] R0[4] G1[0] R1[4] B0[7] R0[3] B1[7] R1[3] B0[6] R0[2] B1[6] R1[2] B0[5] R0[1] B1[5] R1[1] B0[4] R0[0] B1[4] R1[0] B0[3] G0[7] B1[3] G1[7] G0[0] G0[6] B1[2] G1[6] B0[2] G0[5] B1[1] G1[5] B0[1] G0[4] B1[0] G1[4] B0[0] CH7013A t PH2 t HP2 t t SP2 HP2 t t SP2 HP2 P1a P1b P2a P2b 8 RGB 5-5-5 P0b P1a P1b x G1[2] x R0[4] G1[1] R1[4] R0[3] G1[0] R1[3] R0[2] B1[4] R1[2] R0[1] B1[3] R1[1] R0[0] B1[2] R1[0] G0[4] B1[1] G1[4] G0[3] B1[0] G1[3] 5 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... Rev. 1.5, 9/1/2004 2 16-bit RGB (16-8) P0b P1a P1b A0[7] G1[7] A1[7] A0[6] G1[6] A1[6] A0[5] G1[5] A1[5] A0[4] G1[4] A1[4] A0[3] G1[3] A1[3] A0[2] G1[2] A1[2] A0[1] G1[1] A1[1] A0[0] G1[0] A1[0] R0[7] B1[7] R1[7] R0[6] B1[6] R1[6] R0[5] B1[5] R1[5] R0[4] B1[4] R1[4] R0[3] B1[3] R1[3] R0[2] B1[2] R1[2] R0[1] B0[1] R1[1] R0[0] B0[0] R1[0] 9 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7013A P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 9 ...

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... S[ SP3 P0a P0b 6 RGB 8-bit P0b P0c P1a P1b G0[7] R0[7] B1[7] G1[7] G0[6] R0[6] B1[6] G1[6] G0[5] R0[5] B1[5] G1[5] G0[4] R0[4] B1[4] G1[4] G0[3] R0[3] B1[3] G1[3] G0[2] R0[2] B1[2] G1[2] G0[1] R0[1] B1[1] G1[1] G0[0] R0[0] B1[0] G1[0] CH7013A P2a P2b P3a P3b Cb2[7] Y2[7] Cr2[7] Y3[7] Cb2[6] Y2[6] Cr2[6] Y3[6] Cb2[5] Y2[5] Cr2[5] Y3[5] Cb2[4] Y2[4] Cr2[4] Y3[4] Cb2[3] Y2[3] Cr2[3] Y3[3] Cb2[2] Y2[2] Cr2[2] Y3[2] Cb2[1] Y2[1] Cr2[1] Y3[1] Cb2[0] Y2[0] Cr2[0] Y3[0] t PH3 t HP3 P0c P1a P1b P1c P1c P2a P2b ...

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... TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7013A can render a superior TV image without the added cost of a full frame buffer memory – normally used to implement features such as scaling and full synchronization ...

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... Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer. In addition to the above mode table, the CH7013A also support interlaced input modes, both in CCIR 656 and proprietary formats (see Display Mode Register section.) ...

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... Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the serial port, the CH7013A may be placed in either Normal state, or any of the four power managed states, as listed below (see “Power Management Register” under the Register Descriptions section for programming information). To support power management sensing function (see “ ...

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... CHRONTEL 4.4 Luminance and Chrominance Filter Options The CH7013A contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S- Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and chrominance video bandwidth output is shown in Table 13 ...

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... YSV dB -18 <i> (YSVdB ) n -24 -30 -36 - Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0) 201-0000-041 Rev. 1.5, 9/1/2004 n CH7013A ...

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... CHRONTEL Luminance and Chrominance Filter Options (continued -12 < > i UVfirdB -18 n <i> (UVfirdB ) n -24 -30 -36 - Figure 9: Chrominance Frequency Response n CH7013A 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... Table 14 and shown in Figure 10. (See Figure 13 through 18 for illustrations of composite and S-Video output waveforms.) 4.5.1 CCIR624-3 Compliance The CH7013A is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance: • The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or pseudo-master modes, not in slave mode when the graphics device generates these frequencies. • ...

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... CH7013A 271 272 273 274 275 268 268 269 269 270 270 271 271 ...

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... FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 317 4 3 ° ° ° ° ° ° CH7013A 318 319 320 321 322 323 318 319 320 321 322 323 6 ...

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... Figure 13: NTSC Y (Luminance) Output Waveform (DACG = 0) Color/Level mA V White 26.75 1.003 Yellow 24.62 0.923 Cyan 21.11 0.792 Green 18.98 0.712 Magenta 15.62 0.586 Red 13.49 0.506 Blue 10.14 0.380 Blank/ Black 8.00 0.300 Sync 0.00 0.000 Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1) 20 Color bars: Color bars: CH7013A 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... Cyan/Red 27.51 1.032 Green/Magenta 26.68 1.000 Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1) 201-0000-041 Rev. 1.5, 9/1/2004 Color bars: (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7013A 21 ...

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... Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 18: Composite PAL Video Output Waveform (DACG = 1) 22 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7013A 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... The CH7013A is a fully programmable device, providing for full functional control through a set of registers accessed from the serial port. The CH7013A contains a total of 37 registers, which are listed in Table 15 and described in detail under Register Descriptions. Detailed descriptions of operating modes and their effects are con- tained in the previous section, Functional Description ...

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... CIV5 CIV4 CIV3 VID5 VID4 VID3 TS1 TS0 RSA MS2 MS1 MSO YLM5 YLM4 YLM3 CLM5 CLM4 CLM3 AR5 AR4 AR3 CH7013A ) Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 FY0 FT1 FT0 YSV1 YSV0 YCV IDF2 IDF1 IDF0 XCM0 PCM1 PCM0 SAV2 ...

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... R/W R/W Type Default: This register provides programmable control of the CH7013A display mode, including input resolution (IR[2:0]), output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the table below (default is 640x480 input, NTSC output, 7/8’s scaling). Table 17. Display Modes VOS SR Mode ...

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... Settings for Chroma Channel 00 Minimal Flicker Filtering 01 Slight Flicker Filtering 10 Maximum Flicker Filtering 11 Enable Chroma DotCrawl Reduction NTSC PAL FC1 FC0 FY1 R/W R/W R CH7013A 11 NTSC-J Symbol: FFR Address: 01H Bits FY0 FT1 FT0 R/W R/W R 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... The default setting of 0 uses a four line flicker filter. 201-0000-041 Rev. 1.5, 9/1/2004 Reserved Reserved Reserved R/W R/W R CBW1 CBW0 YPEAK R/W R/W R CH7013A Symbol: Address: 02H Bits Reserved Reserved Reserved R/W R/W R Symbol: VBW Address: 03H Bits YSV1 YSV0 YCV R/W ...

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... Default: The setting of the clock mode bits determines the clocking mechanism used in the CH7013A. The clock modes are shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the XCLK input clock. Note: For what was formerly defined as the master mode, the user must now externally connect the P-OUT clock to the XCLK input pin ...

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... SAV5 SAV4 SAV3 R/W R/W R Reserved Reserved Reserved R/W R/W R CH7013A Symbol: SAV Address: 07H Bits SAV2 SAV1 SAV0 R/W R/W R Symbol: PO Address: 08H Bits SAV8 HP8 VP8 R/W R/W R ...

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... BL4 BL3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7013A Symbol: BLR Address: 09H Bits BL2 BL1 BL0 R/W R/W R Symbol: HPR Address: 0AH Bits HP2 HP1 HP0 R/W R/W R Symbol: VPR Address: 0BH ...

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... VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low, and a value of one means the vertical sync is active high. • SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7013A. A value of one means that H and V sync are output from the CH7013A. ...

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... Default: This register provides control of the contrast enhancement feature of the CH7013A, according to the table below setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of 011 ...

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... The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7013A is operating in master or pseudo-master clock mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value ...

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... The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase detector, when the CH7013A is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master and pseudo- ...

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... FSCI[3:0] When the CH7013A is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21H should be set to “0”, and the CFRB bit in register 06H should be set to “1”. ...

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... PAL-Nc (Argentina) “Normal Dot Crawl” 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 569,807,942 867,513,766 201-0000-041 Rev. 1.5, 9/1/2004 CH7013A PAL-M 762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 516,418,687 451,866,351 622,468,953 544,660,334 508,349,645 521,384,251 469,245,826 428,083,911 568,782,819 ...

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... PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs. Mode is shown below PLLCPI PLLCHI controls the charge pump current of the PLL. The default value should be used. 201-0000-041 Rev. 1.5, 9/1/2004 PLLCPI PLLCAP PLLS R/W R/W R CH7013A Symbol: PLLC Address: 20H Bits PLL5VD PLL5VA MEM5V R/W R/W R ...

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... Reserved Symbol: Type: Default: 38 PLLCAP Value Reserved CIV25 CIV24 R R CH7013A Symbol: CIVC Address: 21H Bits CIVH1 CIVH0 ACIV R/W R/W R 201-0000-041 Rev. 1.5, 9/1/2004 ...

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... Default: This read-only register contains a 8-bit value indicating the identification number assigned to this version of the CH7013A. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming. Address Register ...

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... S-Video & composite outputs) DVDD (3.3V) current RSET = 360 Ω, VREF = 1.235V, and NTSC CCIR601 operation. 40 Min - 0.5 1 GND - 0 Min 4.75 4.75 3 Min Typ 9 9 33.89 105 25 CH7013A Typ Max Units 7.0 V VDD + 0.5 V Indefinite Sec °C 125 °C 150 °C 150 °C 220 Typ Max Units 5.00 5. ...

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... CHRONTEL Table 34. CH7013A Supply Current Characteristics Description Normal Operation IDD1 IDD2 IDD3 Normal Operation S-Video only IDD1 IDD2 IDD3 Normal Operation, composite only IDD1 IDD2 IDD3 Partial Power Down IDD1 IDD2 IDD3 Full Power Down Total of DVDD, AVDD, & VDD supply current ...

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... Pixel Clock High Time PH3 tdc3 Pixel Clock Duty Cycle (t 42 Test Condition IOL = 3.2 mA GND-0.5 GND-0.5 IOL = - 400 µA IOL = 3.2 mA Min PH1 PH2 PH3 P3 CH7013A Min Typ Max Unit 0.4 V 3.4 DVDDV (1) + 0.5 V 1.4 V 2.5 (1) 0.5 V DVDDV + 0.8 V 2.8 V 0.2 V Typ Max Unit 50 ...

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... DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. 2. VREF: I/O Reference voltage. In general cases, VREF = DVDDV/2. 201-0000-041 Rev. 1.5, 9/1/2004 t7 64 PIXELS 1 VGA Line t5 t2 DVDDV (2) = 1. (D[11:0], H, & (D[11:0], H, & V) CH7013A P0a P0b P1a P1b P2a P2b t5 Min Typ Max Unit (1) (1) -0 ...

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... DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. 2. VREF: I/O Reference voltage. In general cases, VREF = DVDDV/ PIXELS 1 VGA Line t5 t2 DVDDV (2) = 1.65 V (2) ) (2) ( (D[11:0], H, & VREF ) (2) ) (2) ( (D[11:0], H, & VREF ) CH7013A P0a P0b P1a P1b P2a P2b t5 Min Typ Max Unit (1) (1) -0.2 DVDDV +0.2 V -0.2 0.2 V ...

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... MIN 11.80 9.90 Milli- meters MAX 12.20 10.10 MIN 0.465 0.390 Inches MAX 0.480 0.398 201-0000-041 Rev. 1.5, 9/1/2004 SYMBOL 0.30 1.35 0.05 0.80 0.40 1.45 0.15 0.012 0.0531 0.00197 0.031 0.016 0.0571 0.0059 CH7013A LEAD E .004 0.50 0° 1.016 0.75 0.17 7° 0.0197 0° 0.040 0.0295 0.0067 7° 45 ...

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... CHRONTEL EVISION ISTORY Rev. # Date Section 1.0 6/14/00 All 1.5 9/1/ Description First official release of CH7013A datasheet, Rev. 1.0 Current consumption updated. 201-0000-041 Rev. 1.5, 9/1/2004 CH7013A ...

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... Rev. 1.5, 9/1/2004 Disclaimer ORDERING INFORMATION Package type Number of pins LQFP 44 LQFP, Tape&Reel 44 LQFP, Lead free 44 LQFP, Lead free, 44 Tape&Reel Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7013A Voltage supply 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 47 ...